Index of /archive/邏設實驗/108黃元豪/final project/old/

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lab11_VGA_source/                                  21-Mar-2026 11:06       -
08_Speaker.pdf                                     21-Mar-2026 11:06    659K
09_Keyboard.pdf                                    21-Mar-2026 11:06    927K
10_Electronic_Organ.pdf                            21-Mar-2026 11:06    278K
11_VGA.pdf                                         21-Mar-2026 11:06      2M
12_random_number_generator.pdf                     21-Mar-2026 11:06    566K
FF_final_project.pdf                               21-Mar-2026 11:06    243K
Final Project Proposal .doc                        21-Mar-2026 11:06     60K
Final-Project-Proposal.doc                         21-Mar-2026 11:06     60K
For Loop - VHDL _ Verilog Example.pdf              21-Mar-2026 11:06    112K
Project Examples.pdf                               21-Mar-2026 11:06    128K
Specification.txt                                  21-Mar-2026 11:06     525
final_project_TOP.v                                21-Mar-2026 11:06     27K
一些常見io定義.txt                                       21-Mar-2026 11:06     12K