Index of /archive/邏設實驗/110李濬屹/Lab 2/Visio/

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FPGA_1.vsd                                         21-Mar-2026 11:06    145K
FPGA_2.vsd                                         21-Mar-2026 11:06     78K
Q1_gates.vsd                                       21-Mar-2026 11:06     99K
Q1_nand_implement.vsd                              21-Mar-2026 11:06    131K
Q1_ripple_carry_adder.vsd                          21-Mar-2026 11:06    115K
Q2_4bit8x1mux.vsd                                  21-Mar-2026 11:06     90K
Q2_8bitor_all.vsd                                  21-Mar-2026 11:06     89K
Q2_ADD_SUB_BITWISEAND_BITWISEOR.vsd                21-Mar-2026 11:06     86K
Q2_buffer_XNOR_NOR_HA_FA.vsd                       21-Mar-2026 11:06     85K
Q2_compare.vsd                                     21-Mar-2026 11:06     80K
Q2_comparegt_eq_4bitand.vsd                        21-Mar-2026 11:06     83K
Q2_ls_rs.vsd                                       21-Mar-2026 11:06     81K
Q2_not_and_or_xor.vsd                              21-Mar-2026 11:06     84K
Q2_universal_gate.vsd                              21-Mar-2026 11:06     80K