../ advance/ 21-Mar-2026 11:06 - basic/ 21-Mar-2026 11:06 - 電路圖/ 21-Mar-2026 11:06 - Lab 1 Gate-Level Modeling.docx 21-Mar-2026 11:06 1M Lab 1 Gate-Level Verilog.pdf 21-Mar-2026 11:06 2M Lab1_Team30_Report.docx 21-Mar-2026 11:06 600K Lab1_Team30_Report.pdf 21-Mar-2026 11:06 862K