| dwncntr_2d Project Status (03/28/2016 - 17:36:38) | |||
| Project File: | Stop_Watch.xise | Parser Errors: | No Errors |
| Module Name: | dwncntr_2d | Implementation State: | Programming File Not Generated |
| Target Device: | xc6slx16-3csg324 |
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| Product Version: | ISE 14.7 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice Registers | 6 | 18224 | 0% | |
| Number of Slice LUTs | 8 | 9112 | 0% | |
| Number of fully used LUT-FF pairs | 0 | 14 | 0% | |
| Number of bonded IOBs | 11 | 232 | 4% | |
| Number of BUFG/BUFGCTRLs | 1 | 16 | 6% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 週六 三月 26 17:17:48 2016 | ||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | 週日 三月 27 16:44:11 2016 | |
| WebTalk Report | Current | 週一 三月 28 17:36:34 2016 | |
| WebTalk Log File | Current | 週一 三月 28 17:36:37 2016 | |