Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) dfb930b1acd743ac8ca2cd659d1b1b76.1897D4EBBBE446CB9901E0F1D02DFB43.16 Target Package: csg324
Registration ID 211160026_0_0_772 Target Speed: -3
Date Generated 2016-05-03T16:53:29 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 2394 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 2394 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=1
  • 20-bit comparator equal=1
 Counters=4
  • 20-bit up counter=1
  • 4-bit down counter=2
  • 9-bit up counter=1
 Multiplexers=6
  • 1-bit 16-to-1 multiplexer=2
  • 16-bit 2-to-1 multiplexer=2
  • 20-bit 2-to-1 multiplexer=2
 Registers=1
  • Flip-Flops=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=12
  • AGG_IO=12
  • AGG_LOCED_IO=12
  • AGG_SLICE=14
  • NUM_BONDED_IOB=12
  • NUM_BSFULL=33
  • NUM_BSLUTONLY=14
  • NUM_BSUSED=47
  • NUM_BUFG=1
  • NUM_LOCED_IOB=12
  • NUM_LOGIC_O5ANDO6=26
  • NUM_LOGIC_O5ONLY=7
  • NUM_LOGIC_O6ONLY=12
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_DRIVES_OTHERS=1
  • NUM_LUT_RT_EXO6=2
  • NUM_LUT_RT_O6=7
  • NUM_SLICEL=11
  • NUM_SLICEX=3
  • NUM_SLICE_CARRY4=10
  • NUM_SLICE_CONTROLSET=3
  • NUM_SLICE_CYINIT=82
  • NUM_SLICE_F7MUX=2
  • NUM_SLICE_F8MUX=1
  • NUM_SLICE_FF=34
  • NUM_SLICE_UNUSEDCTRL=4
  • NUM_UNUSABLE_FF_BELS=14
 		NetStatistics
  • NumNets_Active=71
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=2
  • NumNodesOfType_Active_BOUNCEIN=10
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=2
  • NumNodesOfType_Active_CLKPIN=10
  • NumNodesOfType_Active_CLKPINFEED=2
  • NumNodesOfType_Active_CNTRLPIN=6
  • NumNodesOfType_Active_DOUBLE=41
  • NumNodesOfType_Active_GENERIC=18
  • NumNodesOfType_Active_GLOBAL=10
  • NumNodesOfType_Active_INPUT=9
  • NumNodesOfType_Active_IOBIN2OUT=11
  • NumNodesOfType_Active_IOBOUTPUT=11
  • NumNodesOfType_Active_LUTINPUT=114
  • NumNodesOfType_Active_OUTBOUND=57
  • NumNodesOfType_Active_OUTPUT=53
  • NumNodesOfType_Active_PADINPUT=4
  • NumNodesOfType_Active_PADOUTPUT=7
  • NumNodesOfType_Active_PINBOUNCE=25
  • NumNodesOfType_Active_PINFEED=135
  • NumNodesOfType_Active_QUAD=43
  • NumNodesOfType_Active_REGINPUT=1
  • NumNodesOfType_Active_SINGLE=60
  • NumNodesOfType_Vcc_GENERIC=1
  • NumNodesOfType_Vcc_HVCCOUT=11
  • NumNodesOfType_Vcc_IOBIN2OUT=1
  • NumNodesOfType_Vcc_IOBOUTPUT=1
  • NumNodesOfType_Vcc_KVCCOUT=3
  • NumNodesOfType_Vcc_LUTINPUT=33
  • NumNodesOfType_Vcc_PADINPUT=1
  • NumNodesOfType_Vcc_PINBOUNCE=7
  • NumNodesOfType_Vcc_PINFEED=34
  • NumNodesOfType_Vcc_REGINPUT=7
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=6
  • IOB-IOBS=6
  • SLICEL-SLICEM=7
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=10
  • FF_SR=1
  • HARD0=2
  • INVERTER=1
  • IOB=12
  • IOB_IMUX=7
  • IOB_INBUF=7
  • IOB_OUTBUF=5
  • LUT5=33
  • LUT6=47
  • PAD=12
  • REG_SR=33
  • SELMUX2_1=3
  • SLICEL=11
  • SLICEX=3
 
Configuration Data
FF_SR
  • CK=[CK:1] [CK_INV:0]
  • SRINIT=[SRINIT0:1]
  • SYNC_ATTR=[ASYNC:1]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:5]
  • SLEW=[SLOW:5]
  • SUSPEND=[3STATE:5]
 REG_SR
  • CK=[CK:33] [CK_INV:0]
  • LATCH_OR_FF=[FF:33]
  • SRINIT=[SRINIT0:33]
  • SYNC_ATTR=[ASYNC:33]
 SLICEL
  • CLK=[CLK:8] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:2] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=8
  • CO2=1
  • CO3=8
  • CYINIT=2
  • DI0=9
  • DI1=9
  • DI2=9
  • DI3=7
  • O0=8
  • O1=7
  • O2=7
  • O3=7
  • S0=10
  • S1=9
  • S2=9
  • S3=9
 FF_SR
  • CK=1
  • D=1
  • Q=1
 HARD0
  • 0=2
 INVERTER
  • IN=1
  • OUT=1
 IOB
  • I=7
  • O=5
  • PAD=12
 IOB_IMUX
  • I=6
  • I_B=1
  • OUT=7
 IOB_INBUF
  • OUT=7
  • PAD=7
 IOB_OUTBUF
  • IN=5
  • OUT=5
 LUT5
  • A2=1
  • A3=4
  • A4=3
  • A5=4
  • O5=33
 LUT6
  • A1=7
  • A2=8
  • A3=10
  • A4=45
  • A5=32
  • A6=44
  • O6=47
 PAD
  • PAD=12
 REG_SR
  • CK=33
  • D=33
  • Q=33
  • SR=21
 SELMUX2_1
  • 0=1
  • 1=3
  • OUT=3
  • S0=3
 SLICEL
  • A1=2
  • A2=2
  • A3=2
  • A4=10
  • A5=7
  • A6=10
  • AQ=8
  • AX=2
  • B1=2
  • B2=2
  • B3=2
  • B4=9
  • B5=7
  • B6=9
  • BMUX=1
  • BQ=7
  • BX=3
  • C1=1
  • C2=1
  • C3=1
  • C4=10
  • C5=8
  • C6=10
  • CIN=8
  • CLK=8
  • CMUX=1
  • COUT=8
  • CQ=7
  • CX=2
  • D=1
  • D1=2
  • D2=2
  • D3=2
  • D4=9
  • D5=6
  • D6=9
  • DQ=7
  • DX=1
  • SR=5
 SLICEX
  • A=1
  • A3=1
  • A4=2
  • A5=1
  • A6=2
  • AMUX=1
  • AQ=1
  • B=1
  • B3=1
  • B4=2
  • B5=1
  • B6=1
  • BMUX=1
  • BQ=1
  • C4=1
  • C6=1
  • CLK=2
  • CQ=1
  • D=1
  • D2=1
  • D3=2
  • D4=2
  • D5=2
  • D6=2
  • DMUX=2
  • DQ=1
  • SR=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 91 72 0 0 0 0 0
bitgen 97 96 0 0 0 0 0
map 104 102 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngdbuild 112 112 0 0 0 0 0
par 101 101 0 0 0 0 0
trce 101 101 0 0 0 0 0
xst 282 279 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_design_properties.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store non-default values only
PROP_SelectedInstanceHierarchicalPath=/freq_div PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2016-04-30T22:12:53 PROP_intWbtProjectID=1897D4EBBBE446CB9901E0F1D02DFB43
PROP_intWbtProjectIteration=16 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.freq_div PROP_AutoTop=false
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx16
PROP_DevFamilyPMName=spartan6 PROP_ISimSimulationRunTime_behav_tb=5000 ns
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=7
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=13 NGDBUILD_NUM_FDC=21 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=7 NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=8 NGDBUILD_NUM_LUT2=24
NGDBUILD_NUM_LUT3=9 NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_LUT5=1 NGDBUILD_NUM_LUT6=6
NGDBUILD_NUM_MUXCY=35 NGDBUILD_NUM_MUXF7=2 NGDBUILD_NUM_MUXF8=1 NGDBUILD_NUM_OBUF=5
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=29
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=13 NGDBUILD_NUM_FDC=21 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=7 NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=8 NGDBUILD_NUM_LUT2=24
NGDBUILD_NUM_LUT3=9 NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_LUT5=1 NGDBUILD_NUM_LUT6=6
NGDBUILD_NUM_MUXCY=35 NGDBUILD_NUM_MUXF7=2 NGDBUILD_NUM_MUXF8=1 NGDBUILD_NUM_OBUF=5
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=29
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=609 ms, 26220 KB
Total Signals=17
Total Nets=20
Total Blocks=3
Total Processes=14
Total Simulation Time=5 us
Simulation Resource Usage=0.15625 sec, 339546 KB
Simulation Mode=gui
Hardware CoSim=0