add1 Project Status (04/11/2016 - 15:00:07)
Project File: Simple_Calculator.xise Parser Errors: No Errors
Module Name: scan_ctl Implementation State: Programming File Not Generated
Target Device: xc6slx16-3csg324
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Date週六 四月 9 16:01:32 2016
WebTalk ReportCurrent週一 四月 11 14:59:59 2016
WebTalk Log FileCurrent週一 四月 11 15:00:06 2016

Date Generated: 04/11/2016 - 15:00:07
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