welcome Project Status (04/06/2016 - 23:29:44)
Project File: Shifting_Displays.xise Parser Errors: No Errors
Module Name: welcome Implementation State: Mapped (Failed)
Target Device: xc6slx16-3csg324
  • Errors:
X 4 Errors (0 new)
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent週三 四月 6 23:29:31 20160012 Infos (12 new)
Translation ReportCurrent週三 四月 6 23:29:38 2016000
Map ReportCurrent週三 四月 6 23:29:43 2016X 4 Errors (0 new)01 Info (0 new)
Place and Route ReportOut of Date週五 三月 25 19:51:39 201603 Warnings (0 new)3 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportOut of Date週五 三月 25 19:51:44 2016004 Infos (0 new)
Bitgen ReportOut of Date週五 三月 25 19:51:53 2016000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Date週二 三月 22 17:32:14 2016
WebTalk ReportOut of Date週五 三月 25 19:51:54 2016
WebTalk Log FileOut of Date週五 三月 25 19:52:01 2016

Date Generated: 04/06/201