LFSR Project Status (05/30/2016 - 20:33:23)
Project File: LFSR.xise Parser Errors: No Errors
Module Name: LFSR Implementation State: Synthesized
Target Device: xc6slx16-3csg324
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 20 18224 0%
Number of Slice LUTs 42 9112 0%
Number of fully used LUT-FF pairs 18 44 40%
Number of bonded IOBs 8 232 3%
Number of BUFG/BUFGCTRLs 1 16 6%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent週一 五月 30 12:02:26 2016   
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrent週一 五月 30 20:06:14 2016
WebTalk ReportCurrent週一 五月 30 20:33:16 2016
WebTalk Log FileCurrent週一 五月 30 20:33:23 2016

Date Generated: 05/30/2016 - 20:33:23