Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) dfb930b1acd743ac8ca2cd659d1b1b76.1E8E7369CB4347A690174FA7C30300B8.1 Target Package: csg324
Registration ID 211160026_0_0_772 Target Speed: -3
Date Generated 2016-05-23T19:45:43 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 2394 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 2394 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=20
  • 2-bit adder=1
  • 3-bit subtractor=1
  • 4-bit adder=8
  • 6-bit adder=1
  • 7-bit subtractor=1
  • 8-bit subtractor=2
  • 9-bit subtractor=6
 Comparators=1
  • 3-bit comparator lessequal=1
 Counters=6
  • 19-bit up counter=1
  • 2-bit up counter=1
  • 3-bit up counter=1
  • 6-bit up counter=2
  • 8-bit up counter=1
 FSMs=2 Logic shifters=10
  • 496-bit shifter logical right=10
 Multiplexers=575
  • 1-bit 2-to-1 multiplexer=10
  • 1-bit 512-to-1 multiplexer=8
  • 10-bit 2-to-1 multiplexer=1
  • 11-bit 2-to-1 multiplexer=1
  • 12-bit 2-to-1 multiplexer=1
  • 13-bit 2-to-1 multiplexer=1
  • 14-bit 2-to-1 multiplexer=1
  • 15-bit 2-to-1 multiplexer=1
  • 16-bit 12-to-1 multiplexer=8
  • 16-bit 2-to-1 multiplexer=1
  • 17-bit 2-to-1 multiplexer=1
  • 18-bit 2-to-1 multiplexer=1
  • 19-bit 2-to-1 multiplexer=1
  • 2-bit 2-to-1 multiplexer=4
  • 20-bit 2-to-1 multiplexer=1
  • 21-bit 2-to-1 multiplexer=1
  • 22-bit 2-to-1 multiplexer=1
  • 23-bit 2-to-1 multiplexer=1
  • 24-bit 2-to-1 multiplexer=1
  • 25-bit 2-to-1 multiplexer=1
  • 26-bit 2-to-1 multiplexer=1
  • 27-bit 2-to-1 multiplexer=1
  • 28-bit 2-to-1 multiplexer=1
  • 29-bit 2-to-1 multiplexer=1
  • 3-bit 2-to-1 multiplexer=1
  • 30-bit 2-to-1 multiplexer=1
  • 31-bit 2-to-1 multiplexer=1
  • 32-bit 2-to-1 multiplexer=1
  • 33-bit 2-to-1 multiplexer=1
  • 34-bit 2-to-1 multiplexer=1
  • 35-bit 2-to-1 multiplexer=1
  • 36-bit 2-to-1 multiplexer=1
  • 37-bit 2-to-1 multiplexer=1
  • 38-bit 2-to-1 multiplexer=1
  • 39-bit 2-to-1 multiplexer=1
  • 4-bit 2-to-1 multiplexer=25
  • 40-bit 2-to-1 multiplexer=1
  • 41-bit 2-to-1 multiplexer=1
  • 42-bit 2-to-1 multiplexer=1
  • 43-bit 2-to-1 multiplexer=1
  • 44-bit 2-to-1 multiplexer=1
  • 45-bit 2-to-1 multiplexer=1
  • 46-bit 2-to-1 multiplexer=1
  • 47-bit 2-to-1 multiplexer=1
  • 48-bit 2-to-1 multiplexer=1
  • 49-bit 2-to-1 multiplexer=1
  • 5-bit 2-to-1 multiplexer=1
  • 50-bit 2-to-1 multiplexer=1
  • 51-bit 2-to-1 multiplexer=1
  • 52-bit 2-to-1 multiplexer=1
  • 53-bit 2-to-1 multiplexer=1
  • 54-bit 2-to-1 multiplexer=1
  • 55-bit 2-to-1 multiplexer=1
  • 56-bit 2-to-1 multiplexer=1
  • 57-bit 2-to-1 multiplexer=1
  • 58-bit 2-to-1 multiplexer=1
  • 59-bit 2-to-1 multiplexer=1
  • 6-bit 2-to-1 multiplexer=3
  • 60-bit 2-to-1 multiplexer=1
  • 61-bit 2-to-1 multiplexer=1
  • 62-bit 2-to-1 multiplexer=1
  • 63-bit 2-to-1 multiplexer=1
  • 64-bit 2-to-1 multiplexer=450
  • 7-bit 2-to-1 multiplexer=1
  • 8-bit 2-to-1 multiplexer=9
  • 9-bit 2-to-1 multiplexer=1
 Registers=576
  • Flip-Flops=576
 		MiscellaneousStatistics
  • AGG_BONDED_IO=18
  • AGG_IO=18
  • AGG_LOCED_IO=18
  • AGG_SLICE=357
  • NUM_BONDED_IOB=18
  • NUM_BSFULL=640
  • NUM_BSLUTONLY=495
  • NUM_BSREGONLY=27
  • NUM_BSUSED=1162
  • NUM_BUFG=3
  • NUM_LOCED_IOB=18
  • NUM_LOGIC_O5ANDO6=39
  • NUM_LOGIC_O5ONLY=18
  • NUM_LOGIC_O6ONLY=1077
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O5=1
  • NUM_LUT_RT_O6=18
  • NUM_RAMB16BWER=1
  • NUM_SLICEL=75
  • NUM_SLICEX=282
  • NUM_SLICE_CARRY4=7
  • NUM_SLICE_CONTROLSET=11
  • NUM_SLICE_CYINIT=1194
  • NUM_SLICE_F7MUX=68
  • NUM_SLICE_FF=674
  • NUM_SLICE_UNUSEDCTRL=166
  • NUM_UNUSABLE_FF_BELS=38
  • Xilinx Core blk_mem_gen_v7_3, Xilinx CORE Generator 14.7=1
 		NetStatistics
  • NumNets_Active=1286
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=34
  • NumNodesOfType_Active_BOUNCEIN=262
  • NumNodesOfType_Active_BUFGOUT=3
  • NumNodesOfType_Active_BUFHINP2OUT=9
  • NumNodesOfType_Active_CLKPIN=191
  • NumNodesOfType_Active_CLKPINFEED=17
  • NumNodesOfType_Active_CNTRLPIN=346
  • NumNodesOfType_Active_DOUBLE=2337
  • NumNodesOfType_Active_GENERIC=18
  • NumNodesOfType_Active_GLOBAL=86
  • NumNodesOfType_Active_INPUT=82
  • NumNodesOfType_Active_IOBIN2OUT=14
  • NumNodesOfType_Active_IOBOUTPUT=14
  • NumNodesOfType_Active_LUTINPUT=6375
  • NumNodesOfType_Active_OUTBOUND=1338
  • NumNodesOfType_Active_OUTPUT=1317
  • NumNodesOfType_Active_PADINPUT=11
  • NumNodesOfType_Active_PADOUTPUT=4
  • NumNodesOfType_Active_PINBOUNCE=994
  • NumNodesOfType_Active_PINFEED=6841
  • NumNodesOfType_Active_QUAD=1028
  • NumNodesOfType_Active_REGINPUT=122
  • NumNodesOfType_Active_SINGLE=2878
  • NumNodesOfType_Gnd_BOUNCEIN=13
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_GENERIC=2
  • NumNodesOfType_Gnd_HGNDOUT=6
  • NumNodesOfType_Gnd_INPUT=39
  • NumNodesOfType_Gnd_IOBIN2OUT=2
  • NumNodesOfType_Gnd_IOBOUTPUT=2
  • NumNodesOfType_Gnd_OUTBOUND=2
  • NumNodesOfType_Gnd_OUTPUT=2
  • NumNodesOfType_Gnd_PADINPUT=2
  • NumNodesOfType_Gnd_PINBOUNCE=18
  • NumNodesOfType_Gnd_PINFEED=35
  • NumNodesOfType_Gnd_REGINPUT=3
  • NumNodesOfType_Gnd_SINGLE=3
  • NumNodesOfType_Vcc_GENERIC=1
  • NumNodesOfType_Vcc_HVCCOUT=38
  • NumNodesOfType_Vcc_INPUT=3
  • NumNodesOfType_Vcc_IOBIN2OUT=1
  • NumNodesOfType_Vcc_IOBOUTPUT=1
  • NumNodesOfType_Vcc_KVCCOUT=1
  • NumNodesOfType_Vcc_LUTINPUT=58
  • NumNodesOfType_Vcc_PADINPUT=1
  • NumNodesOfType_Vcc_PINFEED=62
 SiteStatistics
  • BUFG-BUFGMUX=3
  • IOB-IOBM=9
  • IOB-IOBS=9
  • SLICEL-SLICEM=36
  • SLICEX-SLICEL=57
  • SLICEX-SLICEM=62
 		SiteSummary
  • BUFG=3
  • BUFG_BUFG=3
  • CARRY4=7
  • FF_SR=11
  • HARD0=1
  • IOB=18
  • IOB_IMUX=4
  • IOB_INBUF=4
  • IOB_OUTBUF=14
  • LUT5=58
  • LUT6=1135
  • PAD=18
  • RAMB16BWER=1
  • RAMB16BWER_RAMB16BWER=1
  • REG_SR=663
  • SELMUX2_1=68
  • SLICEL=75
  • SLICEX=282
 
Configuration Data
FF_SR
  • CK=[CK:11] [CK_INV:0]
  • SRINIT=[SRINIT0:11]
  • SYNC_ATTR=[ASYNC:11]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:14]
  • SLEW=[SLOW:14]
  • SUSPEND=[3STATE:14]
 RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEB=[REGCEB_INV:0] [REGCEB:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:1] [WEB0_INV:0]
  • WEB1=[WEB1:1] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:1]
  • WEB3=[WEB3:1] [WEB3_INV:0]
 RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • DATA_WIDTH_A=[36:1]
  • DATA_WIDTH_B=[36:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • EN_RSTRAM_A=[FALSE:1]
  • EN_RSTRAM_B=[FALSE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEB=[REGCEB_INV:0] [REGCEB:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:1] [WEB0_INV:0]
  • WEB1=[WEB1:1] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:1]
  • WEB3=[WEB3:1] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
 REG_SR
  • CK=[CK:663] [CK_INV:0]
  • LATCH_OR_FF=[FF:663]
  • SRINIT=[SRINIT0:659] [SRINIT1:4]
  • SYNC_ATTR=[ASYNC:663]
 SLICEL
  • CLK=[CLK:11] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:180] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=3
  • O=3
 BUFG_BUFG
  • I0=3
  • O=3
 CARRY4
  • CIN=5
  • CO3=5
  • CYINIT=2
  • DI0=7
  • DI1=7
  • DI2=6
  • DI3=5
  • O0=7
  • O1=7
  • O2=7
  • O3=6
  • S0=7
  • S1=7
  • S2=7
  • S3=6
 FF_SR
  • CE=5
  • CK=11
  • D=11
  • Q=11
  • SR=11
 HARD0
  • 0=1
 IOB
  • I=4
  • O=14
  • PAD=18
 IOB_IMUX
  • I=4
  • OUT=4
 IOB_INBUF
  • OUT=4
  • PAD=4
 IOB_OUTBUF
  • IN=14
  • OUT=14
 LUT5
  • A1=15
  • A2=29
  • A3=30
  • A4=32
  • A5=22
  • O5=58
 LUT6
  • A1=960
  • A2=1033
  • A3=1074
  • A4=1117
  • A5=1099
  • A6=1131
  • O6=1135
 PAD
  • PAD=18
 RAMB16BWER
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB0=1
  • ADDRB1=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB2=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIA0=1
  • DIA1=1
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=1
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=1
  • DIA30=1
  • DIA31=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=1
  • DIPA1=1
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA16=1
  • DOA17=1
  • DOA18=1
  • DOA19=1
  • DOA2=1
  • DOA20=1
  • DOA21=1
  • DOA22=1
  • DOA23=1
  • DOA24=1
  • DOA25=1
  • DOA26=1
  • DOA27=1
  • DOA28=1
  • DOA29=1
  • DOA3=1
  • DOA30=1
  • DOA31=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOB0=1
  • DOB1=1
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB13=1
  • DOB14=1
  • DOB15=1
  • DOB16=1
  • DOB17=1
  • DOB18=1
  • DOB19=1
  • DOB2=1
  • DOB20=1
  • DOB21=1
  • DOB22=1
  • DOB23=1
  • DOB24=1
  • DOB25=1
  • DOB26=1
  • DOB27=1
  • DOB28=1
  • DOB29=1
  • DOB3=1
  • DOB30=1
  • DOB31=1
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=1
  • ENB=1
  • REGCEA=1
  • REGCEB=1
  • RSTA=1
  • RSTB=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
 RAMB16BWER_RAMB16BWER
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB0=1
  • ADDRB1=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB2=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIA0=1
  • DIA1=1
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=1
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=1
  • DIA30=1
  • DIA31=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=1
  • DIPA1=1
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA16=1
  • DOA17=1
  • DOA18=1
  • DOA19=1
  • DOA2=1
  • DOA20=1
  • DOA21=1
  • DOA22=1
  • DOA23=1
  • DOA24=1
  • DOA25=1
  • DOA26=1
  • DOA27=1
  • DOA28=1
  • DOA29=1
  • DOA3=1
  • DOA30=1
  • DOA31=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOB0=1
  • DOB1=1
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB13=1
  • DOB14=1
  • DOB15=1
  • DOB16=1
  • DOB17=1
  • DOB18=1
  • DOB19=1
  • DOB2=1
  • DOB20=1
  • DOB21=1
  • DOB22=1
  • DOB23=1
  • DOB24=1
  • DOB25=1
  • DOB26=1
  • DOB27=1
  • DOB28=1
  • DOB29=1
  • DOB3=1
  • DOB30=1
  • DOB31=1
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=1
  • ENB=1
  • REGCEA=1
  • REGCEB=1
  • RSTA=1
  • RSTB=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
 REG_SR
  • CE=581
  • CK=663
  • D=663
  • Q=663
  • SR=663
 SELMUX2_1
  • 0=68
  • 1=68
  • OUT=68
  • S0=68
 SLICEL
  • A=31
  • A1=16
  • A2=29
  • A3=31
  • A4=38
  • A5=33
  • A6=39
  • AMUX=3
  • AQ=11
  • AX=4
  • B=25
  • B1=13
  • B2=25
  • B3=26
  • B4=32
  • B5=27
  • B6=32
  • BMUX=2
  • BQ=7
  • BX=1
  • C=8
  • C1=61
  • C2=70
  • C3=70
  • C4=75
  • C5=70
  • C6=74
  • CE=3
  • CIN=5
  • CLK=11
  • CMUX=68
  • COUT=5
  • CQ=7
  • CX=70
  • D=16
  • D1=59
  • D2=63
  • D3=63
  • D4=69
  • D5=64
  • D6=74
  • DQ=6
  • SR=11
 SLICEX
  • A=105
  • A1=217
  • A2=225
  • A3=243
  • A4=248
  • A5=246
  • A6=249
  • AMUX=4
  • AQ=171
  • AX=17
  • B=89
  • B1=205
  • B2=215
  • B3=219
  • B4=226
  • B5=224
  • B6=227
  • BMUX=11
  • BQ=154
  • BX=14
  • C=72
  • C1=198
  • C2=205
  • C3=213
  • C4=215
  • C5=218
  • C6=219
  • CE=152
  • CLK=180
  • CMUX=10
  • CQ=160
  • CX=11
  • D=79
  • D1=200
  • D2=208
  • D3=211
  • D4=215
  • D5=217
  • D6=217
  • DMUX=6
  • DQ=147
  • DX=8
  • SR=180
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 133 101 0 0 0 0 0
bitgen 141 138 0 0 0 0 0
map 152 149 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngcbuild 4 4 0 0 0 0 0
ngdbuild 167 166 0 0 0 0 0
par 148 146 0 0 0 0 0
trce 146 146 0 0 0 0 0
xst 375 367 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_design_properties.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store non-default values only
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2016-05-22T23:27:06
PROP_intWbtProjectID=1E8E7369CB4347A690174FA7C30300B8 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx16 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_COREGEN=1 FILE_UCF=1
FILE_VERILOG=13
 
Core Statistics
Core Type=blk_mem_gen_v7_3
c_addra_width=6 c_addrb_width=6 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_default_data=0 c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=masked_value
c_enable_32bit_address=0 c_family=spartan6 c_has_axi_id=0 c_has_ena=0
c_has_enb=0 c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0
c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0
c_has_rsta=0 c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_init_file=BlankString c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0
c_interface_type=0 c_load_init_file=0 c_mem_type=0 c_mux_pipeline_stages=0
c_prim_type=1 c_read_depth_a=64 c_read_depth_b=64 c_read_width_a=64
c_read_width_b=64 c_rst_priority_a=CE c_rst_priority_b=CE c_rst_type=SYNC
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_wea_width=1 c_web_width=1 c_write_depth_a=64
c_write_depth_b=64 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=64
c_write_width_b=64 c_xdevicefamily=spartan6
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=84 NGDBUILD_NUM_FDCE=586
NGDBUILD_NUM_FDP=4 NGDBUILD_NUM_GND=2 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_INV=15
NGDBUILD_NUM_LUT1=18 NGDBUILD_NUM_LUT2=17 NGDBUILD_NUM_LUT3=32 NGDBUILD_NUM_LUT4=65
NGDBUILD_NUM_LUT5=69 NGDBUILD_NUM_LUT6=953 NGDBUILD_NUM_MUXCY=25 NGDBUILD_NUM_MUXF7=68
NGDBUILD_NUM_OBUF=14 NGDBUILD_NUM_RAMB16BWER=1 NGDBUILD_NUM_VCC=2 NGDBUILD_NUM_XORCY=27
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3 NGDBUILD_NUM_FDC=84 NGDBUILD_NUM_FDCE=586 NGDBUILD_NUM_FDP=4
NGDBUILD_NUM_GND=2 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=15
NGDBUILD_NUM_LUT1=18 NGDBUILD_NUM_LUT2=17 NGDBUILD_NUM_LUT3=32 NGDBUILD_NUM_LUT4=65
NGDBUILD_NUM_LUT5=69 NGDBUILD_NUM_LUT6=953 NGDBUILD_NUM_MUXCY=25 NGDBUILD_NUM_MUXF7=68
NGDBUILD_NUM_OBUF=14 NGDBUILD_NUM_RAMB16BWER=1 NGDBUILD_NUM_VCC=2 NGDBUILD_NUM_XORCY=27
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5