lcd2 Project Status
Project File: LCD_Display_II.xise Parser Errors: No Errors
Module Name: lcd2 Implementation State: Programming File Generated
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
3 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 674 18,224 3%  
    Number used as Flip Flops 674      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 1,135 9,112 12%  
    Number used as logic 1,134 9,112 12%  
        Number using O6 output only 1,077      
        Number using O5 output only 18      
        Number using O5 and O6 39      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
    Number used exclusively as route-thrus 1      
        Number with same-slice register load 0      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 357 2,278 15%  
Number of MUXCYs used 28 4,556 1%  
Number of LUT Flip Flop pairs used 1,162      
    Number with an unused Flip Flop 495 1,162 42%  
    Number with an unused LUT 27 1,162 2%  
    Number of fully used LUT-FF pairs 640 1,162 55%  
    Number of unique control sets 11      
    Number of slice register sites lost
        to control set restrictions
38 18,224 1%  
Number of bonded IOBs 18 232 7%  
    Number of LOCed IOBs 18 18 100%  
Number of RAMB16BWERs 1 32 3%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 6.20      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent週一 五月 23 19:43:59 201603 Warnings (0 new)1 Info (0 new)
Translation ReportCurrent週一 五月 23 19:44:06 2016000
Map ReportCurrent週一 五月 23 19:44:55 2016006 Infos (6 new)
Place and Route ReportCurrent週一 五月 23 19:45:16 2016003 Infos (3 new)
Power Report     
Post-PAR Static Timing ReportCurrent週一 五月 23 19:45:25 2016004 Infos (4 new)
Bitgen ReportCurrent週一 五月 23 19:45:41 2016000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent週一 五月 23 19:45:43 2016
WebTalk Log FileCurrent週一 五月 23 19:45:59 2016

Date Generated: 06/01/2016 -