final_exam Project Status
Project File: Final_Exam.xise Parser Errors: No Errors
Module Name: final_exam Implementation State: New
Target Device: xc6slx16-3csg324
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent週一 五月 30 17:57:33 2016
WebTalk Log FileCurrent週一 五月 30 17:57:36 2016

Date Generated: 06/15/2016 - 00:02:06