LED Project Status
Project File:	Final_Exam.xise	Parser Errors:	No Errors
Module Name:	LED	Implementation State:	Mapped
Target Device:	xc6slx16-3csg324	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	週一 五月 30 16:02:43 2016	0	0	0
Translation Report	Current	週一 五月 30 16:02:50 2016	0	0	0
Map Report	Current	週一 五月 30 16:02:56 2016	0	0	0
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 05/30/2016 - 16:08:12 </