Final_Exam Project Status (05/30/2016 - 16:02:57)
Project File: Final_Exam.xise Parser Errors: No Errors
Module Name: Final_Exam Implementation State: Mapped (Stopped)
Target Device: xc6slx16-3csg324
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of bonded IOBs 0 232 0%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent¶g¤@ ¤­¤ë 30 15:34:00 2016   
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 05/30/2016 - 16:03:00