Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) dfb930b1acd743ac8ca2cd659d1b1b76.035926491D124375B7A1494B9E8E95F9.28 Target Package: csg324
Registration ID 211160026_0_0_772 Target Speed: -3
Date Generated 2016-04-25T19:25:09 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 2394 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 2394 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=4
  • 4-bit adder=4
 Counters=1
  • 26-bit up counter=1
 Multiplexers=15
  • 1-bit 2-to-1 multiplexer=2
  • 15-bit 4-to-1 multiplexer=1
  • 4-bit 2-to-1 multiplexer=12
 RAMs=5
  • 16x15-bit single-port distributed Read Only RAM=4
  • 4x4-bit single-port distributed Read Only RAM=1
 Registers=48
  • Flip-Flops=48
 		MiscellaneousStatistics
  • AGG_BONDED_IO=23
  • AGG_IO=23
  • AGG_LOCED_IO=23
  • AGG_SLICE=34
  • NUM_BONDED_IOB=23
  • NUM_BSFULL=52
  • NUM_BSLUTONLY=44
  • NUM_BSREGONLY=14
  • NUM_BSUSED=110
  • NUM_BUFG=1
  • NUM_LOCED_IOB=23
  • NUM_LOGIC_O5ANDO6=18
  • NUM_LOGIC_O5ONLY=22
  • NUM_LOGIC_O6ONLY=51
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_DRIVES_FLOP=4
  • NUM_LUT_RT_EXO5=4
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O5=1
  • NUM_LUT_RT_O6=22
  • NUM_SLICEL=16
  • NUM_SLICEX=18
  • NUM_SLICE_CARRY4=6
  • NUM_SLICE_CONTROLSET=4
  • NUM_SLICE_CYINIT=138
  • NUM_SLICE_F7MUX=10
  • NUM_SLICE_FF=72
  • NUM_SLICE_UNUSEDCTRL=15
 		NetStatistics
  • NumNets_Active=158
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=6
  • NumNodesOfType_Active_BOUNCEIN=23
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=1
  • NumNodesOfType_Active_CLKPIN=19
  • NumNodesOfType_Active_CLKPINFEED=1
  • NumNodesOfType_Active_CNTRLPIN=22
  • NumNodesOfType_Active_DOUBLE=163
  • NumNodesOfType_Active_GENERIC=21
  • NumNodesOfType_Active_GLOBAL=12
  • NumNodesOfType_Active_INPUT=6
  • NumNodesOfType_Active_IOBIN2OUT=17
  • NumNodesOfType_Active_IOBOUTPUT=17
  • NumNodesOfType_Active_LUTINPUT=355
  • NumNodesOfType_Active_OUTBOUND=133
  • NumNodesOfType_Active_OUTPUT=133
  • NumNodesOfType_Active_PADINPUT=14
  • NumNodesOfType_Active_PADOUTPUT=4
  • NumNodesOfType_Active_PINBOUNCE=83
  • NumNodesOfType_Active_PINFEED=408
  • NumNodesOfType_Active_QUAD=34
  • NumNodesOfType_Active_REGINPUT=31
  • NumNodesOfType_Active_SINGLE=260
  • NumNodesOfType_Vcc_GENERIC=5
  • NumNodesOfType_Vcc_HVCCOUT=25
  • NumNodesOfType_Vcc_IOBIN2OUT=5
  • NumNodesOfType_Vcc_IOBOUTPUT=5
  • NumNodesOfType_Vcc_LUTINPUT=41
  • NumNodesOfType_Vcc_PADINPUT=5
  • NumNodesOfType_Vcc_PINFEED=46
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=12
  • IOB-IOBS=11
  • SLICEL-SLICEM=11
  • SLICEX-SLICEL=6
  • SLICEX-SLICEM=3
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=6
  • FF_SR=8
  • HARD0=1
  • INVERTER=3
  • IOB=23
  • IOB_IMUX=4
  • IOB_INBUF=4
  • IOB_OUTBUF=19
  • LUT5=45
  • LUT6=92
  • PAD=23
  • REG_SR=64
  • SELMUX2_1=10
  • SLICEL=16
  • SLICEX=18
 
Configuration Data
FF_SR
  • CK=[CK:8] [CK_INV:0]
  • SRINIT=[SRINIT0:8]
  • SYNC_ATTR=[ASYNC:8]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:19]
  • SLEW=[SLOW:19]
  • SUSPEND=[3STATE:19]
 REG_SR
  • CK=[CK:64] [CK_INV:0]
  • LATCH_OR_FF=[FF:64]
  • SRINIT=[SRINIT0:61] [SRINIT1:3]
  • SYNC_ATTR=[ASYNC:64]
 SLICEL
  • CLK=[CLK:7] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:12] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=5
  • CO3=5
  • CYINIT=1
  • DI0=6
  • DI1=6
  • DI2=6
  • DI3=5
  • O0=6
  • O1=6
  • O2=6
  • O3=6
  • S0=6
  • S1=6
  • S2=6
  • S3=6
 FF_SR
  • CE=4
  • CK=8
  • D=8
  • Q=8
  • SR=8
 HARD0
  • 0=1
 INVERTER
  • IN=3
  • OUT=3
 IOB
  • I=4
  • O=19
  • PAD=23
 IOB_IMUX
  • I=1
  • I_B=3
  • OUT=4
 IOB_INBUF
  • OUT=4
  • PAD=4
 IOB_OUTBUF
  • IN=19
  • OUT=19
 LUT5
  • A1=4
  • A2=13
  • A3=12
  • A4=17
  • A5=19
  • O5=45
 LUT6
  • A1=41
  • A2=49
  • A3=54
  • A4=86
  • A5=66
  • A6=89
  • O6=92
 PAD
  • PAD=23
 REG_SR
  • CE=12
  • CK=64
  • D=64
  • Q=64
  • SR=64
 SELMUX2_1
  • 0=10
  • 1=10
  • OUT=10
  • S0=10
 SLICEL
  • A=2
  • A2=1
  • A3=2
  • A4=8
  • A5=2
  • A6=8
  • AMUX=1
  • AQ=6
  • B=8
  • B1=1
  • B2=8
  • B3=8
  • B4=14
  • B5=9
  • B6=15
  • BMUX=7
  • BQ=7
  • C1=9
  • C2=9
  • C3=9
  • C4=15
  • C5=9
  • C6=15
  • CIN=5
  • CLK=7
  • CMUX=10
  • COUT=5
  • CQ=6
  • CX=10
  • D1=9
  • D2=9
  • D3=9
  • D4=15
  • D5=9
  • D6=14
  • DQ=6
  • SR=7
 SLICEX
  • A=9
  • A1=10
  • A2=11
  • A3=11
  • A4=13
  • A5=14
  • A6=13
  • AMUX=6
  • AQ=10
  • AX=6
  • B=5
  • B1=5
  • B2=5
  • B3=7
  • B4=10
  • B5=12
  • B6=11
  • BMUX=3
  • BQ=11
  • BX=5
  • C=3
  • C1=4
  • C2=5
  • C3=5
  • C4=6
  • C5=8
  • C6=7
  • CE=3
  • CLK=12
  • CMUX=3
  • CQ=9
  • CX=5
  • D=2
  • D1=4
  • D2=4
  • D3=5
  • D4=6
  • D5=7
  • D6=6
  • DMUX=2
  • DQ=9
  • DX=5
  • SR=12
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 76 53 0 0 0 0 0
bitgen 82 81 0 0 0 0 0
map 88 86 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngdbuild 93 93 0 0 0 0 0
par 85 85 0 0 0 0 0
trce 85 85 0 0 0 0 0
xst 247 244 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_design_properties.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store non-default values only PROP_SelectedInstanceHierarchicalPath=/timerTest
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_intProjectCreationTimestamp=2016-04-23T20:47:45 PROP_intWbtProjectID=035926491D124375B7A1494B9E8E95F9
PROP_intWbtProjectIteration=28 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.timerTest PROP_AutoTop=false
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx16
PROP_DevFamilyPMName=spartan6 PROP_ISimSimulationRunTime_behav_tb=540000 ns
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=17
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=53 NGDBUILD_NUM_FDCE=16 NGDBUILD_NUM_FDP=3
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=23
NGDBUILD_NUM_LUT2=11 NGDBUILD_NUM_LUT3=9 NGDBUILD_NUM_LUT4=21 NGDBUILD_NUM_LUT5=5
NGDBUILD_NUM_LUT6=37 NGDBUILD_NUM_MUXCY=23 NGDBUILD_NUM_MUXF7=10 NGDBUILD_NUM_OBUF=19
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=24
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=53 NGDBUILD_NUM_FDCE=16 NGDBUILD_NUM_FDP=3
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=4
NGDBUILD_NUM_LUT1=23 NGDBUILD_NUM_LUT2=11 NGDBUILD_NUM_LUT3=9 NGDBUILD_NUM_LUT4=21
NGDBUILD_NUM_LUT5=5 NGDBUILD_NUM_LUT6=37 NGDBUILD_NUM_MUXCY=23 NGDBUILD_NUM_MUXF7=10
NGDBUILD_NUM_OBUF=19 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=24
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=531 ms, 26460 KB
Total Signals=52
Total Nets=69
Total Blocks=7
Total Processes=36
Total Simulation Time=540 us
Simulation Resource Usage=0.0625 sec, 654155 KB
Simulation Mode=gui
Hardware CoSim=0