| timer Project Status (04/25/2016 - 16:33:53) | |||
| Project File: | Electronic_Clocks_II.xise | Parser Errors: | X 11 Errors |
| Module Name: | timer | Implementation State: | Programming File Generated |
| Target Device: | xc6slx16-3csg324 |
|
|
| Product Version: | ISE 14.7 |
|
|
| Design Goal: | Balanced |
|
|
| Design Strategy: | Xilinx Default (unlocked) |
|
|
| Environment: | System Settings |
|
|
| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice Registers | 51 | 18224 | 0% | |
| Number of Slice LUTs | 68 | 9112 | 0% | |
| Number of fully used LUT-FF pairs | 19 | 100 | 19% | |
| Number of bonded IOBs | 34 | 232 | 14% | |
| Number of BUFG/BUFGCTRLs | 1 | 16 | 6% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 週日 四月 24 00:20:34 2016 | ||||
| Translation Report | Out of Date | 週六 四月 23 23:49:11 2016 | ||||
| Map Report | Out of Date | 週六 四月 23 23:49:24 2016 | ||||
| Place and Route Report | Out of Date | 週六 四月 23 23:49:33 2016 | ||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | Out of Date | 週六 四月 23 23:49:40 2016 | ||||
| Bitgen Report | Out of Date | 週六 四月 23 23:49:54 2016 | ||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Current | 週一 四月 25 16:48:57 2016 | |
| WebTalk Report | Current | 週一 四月 25 16:33:42 2016 | |
| WebTalk Log File | Current | 週一 四月 25 16:33:52 2016 | |