| timer Project Status (04/25/2016 - 19:25:26) | |||
| Project File: | Electronic_Clocks_II.xise | Parser Errors: | No Errors |
| Module Name: | exp1 | Implementation State: | Programming File Generated |
| Target Device: | xc6slx16-3csg324 |
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| Product Version: | ISE 14.7 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice Registers | 88 | 18224 | 0% | |
| Number of Slice LUTs | 164 | 9112 | 1% | |
| Number of fully used LUT-FF pairs | 72 | 180 | 40% | |
| Number of bonded IOBs | 26 | 232 | 11% | |
| Number of BUFG/BUFGCTRLs | 2 | 16 | 12% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 週一 四月 25 19:10:32 2016 | ||||
| Translation Report | Out of Date | 週一 四月 25 18:39:43 2016 | ||||
| Map Report | Out of Date | 週一 四月 25 18:39:52 2016 | ||||
| Place and Route Report | Out of Date | 週一 四月 25 18:40:00 2016 | ||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | Out of Date | 週一 四月 25 18:40:06 2016 | ||||
| Bitgen Report | Out of Date | 週一 四月 25 18:40:15 2016 | ||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | 週一 四月 25 16:48:57 2016 | |
| WebTalk Report | Current | 週一 四月 25 19:25:09 2016 | |
| WebTalk Log File | Current | 週一 四月 25 19:25:25 2016 | |