Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) dfb930b1acd743ac8ca2cd659d1b1b76.99AD9C2F501648E1974D5C7F7F9FF1AC.24 Target Package: csg324
Registration ID 211160026_0_0_772 Target Speed: -3
Date Generated 2016-04-18T19:31:46 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 2394 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 2394 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=8
  • 4-bit adder=8
 Counters=1
  • 26-bit up counter=1
 Multiplexers=29
  • 15-bit 4-to-1 multiplexer=1
  • 4-bit 2-to-1 multiplexer=28
 RAMs=5
  • 16x15-bit single-port distributed Read Only RAM=4
  • 4x4-bit single-port distributed Read Only RAM=1
 Registers=32
  • Flip-Flops=32
 		MiscellaneousStatistics
  • AGG_BONDED_IO=24
  • AGG_IO=24
  • AGG_LOCED_IO=24
  • AGG_SLICE=56
  • NUM_BONDED_IOB=24
  • NUM_BSFULL=48
  • NUM_BSLUTONLY=124
  • NUM_BSREGONLY=1
  • NUM_BSUSED=173
  • NUM_BUFG=2
  • NUM_LOCED_IOB=24
  • NUM_LOGIC_O5ANDO6=32
  • NUM_LOGIC_O5ONLY=14
  • NUM_LOGIC_O6ONLY=125
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=14
  • NUM_SLICEL=18
  • NUM_SLICEX=38
  • NUM_SLICE_CARRY4=4
  • NUM_SLICE_CONTROLSET=2
  • NUM_SLICE_CYINIT=219
  • NUM_SLICE_F7MUX=14
  • NUM_SLICE_FF=52
  • NUM_SLICE_UNUSEDCTRL=37
  • NUM_UNUSABLE_FF_BELS=4
 		NetStatistics
  • NumNets_Active=231
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=5
  • NumNodesOfType_Active_BOUNCEIN=40
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=3
  • NumNodesOfType_Active_CLKPIN=19
  • NumNodesOfType_Active_CLKPINFEED=7
  • NumNodesOfType_Active_CNTRLPIN=19
  • NumNodesOfType_Active_DOUBLE=319
  • NumNodesOfType_Active_GENERIC=23
  • NumNodesOfType_Active_GLOBAL=21
  • NumNodesOfType_Active_INPUT=5
  • NumNodesOfType_Active_IOBIN2OUT=18
  • NumNodesOfType_Active_IOBOUTPUT=18
  • NumNodesOfType_Active_LUTINPUT=843
  • NumNodesOfType_Active_OUTBOUND=208
  • NumNodesOfType_Active_OUTPUT=213
  • NumNodesOfType_Active_PADINPUT=14
  • NumNodesOfType_Active_PADOUTPUT=5
  • NumNodesOfType_Active_PINBOUNCE=106
  • NumNodesOfType_Active_PINFEED=898
  • NumNodesOfType_Active_QUAD=97
  • NumNodesOfType_Active_REGINPUT=19
  • NumNodesOfType_Active_SINGLE=449
  • NumNodesOfType_Vcc_GENERIC=5
  • NumNodesOfType_Vcc_HVCCOUT=31
  • NumNodesOfType_Vcc_IOBIN2OUT=5
  • NumNodesOfType_Vcc_IOBOUTPUT=5
  • NumNodesOfType_Vcc_LUTINPUT=46
  • NumNodesOfType_Vcc_PADINPUT=5
  • NumNodesOfType_Vcc_PINFEED=51
 SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=13
  • IOB-IOBS=11
  • SLICEL-SLICEM=10
  • SLICEX-SLICEL=8
  • SLICEX-SLICEM=5
 		SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=4
  • FF_SR=4
  • HARD0=1
  • INVERTER=1
  • IOB=24
  • IOB_IMUX=5
  • IOB_INBUF=5
  • IOB_OUTBUF=19
  • LUT5=46
  • LUT6=172
  • PAD=24
  • REG_SR=48
  • SELMUX2_1=14
  • SLICEL=18
  • SLICEX=38
 
Configuration Data
FF_SR
  • CK=[CK:4] [CK_INV:0]
  • SRINIT=[SRINIT0:4]
  • SYNC_ATTR=[ASYNC:4]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:19]
  • SLEW=[SLOW:19]
  • SUSPEND=[3STATE:19]
 REG_SR
  • CK=[CK:48] [CK_INV:0]
  • LATCH_OR_FF=[FF:48]
  • SRINIT=[SRINIT0:45] [SRINIT1:3]
  • SYNC_ATTR=[ASYNC:48]
 SLICEL
  • CLK=[CLK:5] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:14] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
 BUFG_BUFG
  • I0=2
  • O=2
 CARRY4
  • CIN=3
  • CO3=3
  • CYINIT=1
  • DI0=4
  • DI1=4
  • DI2=4
  • DI3=3
  • O0=4
  • O1=4
  • O2=4
  • O3=4
  • S0=4
  • S1=4
  • S2=4
  • S3=4
 FF_SR
  • CK=4
  • D=4
  • Q=4
  • SR=4
 HARD0
  • 0=1
 INVERTER
  • IN=1
  • OUT=1
 IOB
  • I=5
  • O=19
  • PAD=24
 IOB_IMUX
  • I=4
  • I_B=1
  • OUT=5
 IOB_INBUF
  • OUT=5
  • PAD=5
 IOB_OUTBUF
  • IN=19
  • OUT=19
 LUT5
  • A1=20
  • A2=27
  • A3=22
  • A4=22
  • A5=23
  • O5=46
 LUT6
  • A1=104
  • A2=123
  • A3=144
  • A4=169
  • A5=152
  • A6=170
  • O6=172
 PAD
  • PAD=24
 REG_SR
  • CK=48
  • D=48
  • Q=48
  • SR=48
 SELMUX2_1
  • 0=14
  • 1=14
  • OUT=14
  • S0=14
 SLICEL
  • A=11
  • A1=10
  • A2=12
  • A3=12
  • A4=16
  • A5=12
  • A6=16
  • AMUX=1
  • AQ=5
  • B=11
  • B1=9
  • B2=10
  • B3=11
  • B4=15
  • B5=11
  • B6=15
  • BMUX=2
  • BQ=4
  • C1=11
  • C2=14
  • C3=14
  • C4=18
  • C5=14
  • C6=18
  • CIN=3
  • CLK=5
  • CMUX=14
  • COUT=3
  • CQ=4
  • CX=14
  • D1=11
  • D2=11
  • D3=11
  • D4=15
  • D5=11
  • D6=17
  • DQ=4
  • SR=5
 SLICEX
  • A=24
  • A1=19
  • A2=25
  • A3=26
  • A4=31
  • A5=30
  • A6=30
  • AMUX=11
  • AQ=12
  • AX=2
  • B=23
  • B1=21
  • B2=24
  • B3=26
  • B4=27
  • B5=27
  • B6=27
  • BMUX=6
  • BQ=6
  • BX=2
  • C=16
  • C1=19
  • C2=22
  • C3=24
  • C4=24
  • C5=24
  • C6=24
  • CLK=14
  • CMUX=3
  • CQ=8
  • D=19
  • D1=17
  • D2=19
  • D3=20
  • D4=23
  • D5=23
  • D6=23
  • DMUX=8
  • DQ=5
  • DX=1
  • SR=14
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 54 44 0 0 0 0 0
bitgen 55 55 0 0 0 0 0
map 57 56 0 0 0 0 0
ngdbuild 57 57 0 0 0 0 0
par 55 55 0 0 0 0 0
trce 55 55 0 0 0 0 0
xst 160 158 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_design_properties.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store non-default values only
PROP_SelectedInstanceHierarchicalPath=/min_secTest PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2016-04-17T08:28:05 PROP_intWbtProjectID=99AD9C2F501648E1974D5C7F7F9FF1AC
PROP_intWbtProjectIteration=24 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.min_secTest PROP_AutoTop=false
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx16
PROP_DevFamilyPMName=spartan6 PROP_ISimSimulationRunTime_behav_tb=9000 ns
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=17
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=49 NGDBUILD_NUM_FDP=3
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LUT1=15
NGDBUILD_NUM_LUT2=8 NGDBUILD_NUM_LUT3=30 NGDBUILD_NUM_LUT4=17 NGDBUILD_NUM_LUT5=32
NGDBUILD_NUM_LUT6=96 NGDBUILD_NUM_MUXCY=15 NGDBUILD_NUM_MUXF7=14 NGDBUILD_NUM_OBUF=19
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=16
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FDC=49 NGDBUILD_NUM_FDP=3 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LUT1=15
NGDBUILD_NUM_LUT2=8 NGDBUILD_NUM_LUT3=30 NGDBUILD_NUM_LUT4=17 NGDBUILD_NUM_LUT5=32
NGDBUILD_NUM_LUT6=96 NGDBUILD_NUM_MUXCY=15 NGDBUILD_NUM_MUXF7=14 NGDBUILD_NUM_OBUF=19
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=16
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=452 ms, 26444 KB
Total Signals=57
Total Nets=57
Total Blocks=9
Total Processes=41
Total Simulation Time=9 us
Simulation Resource Usage=0.28125 sec, 339566 KB
Simulation Mode=gui
Hardware CoSim=0