min_sec Project Status (04/18/2016 - 15:08:08)
Project File:	Electronic_Clocks.xise	Parser Errors:	No Errors
Module Name:	timer	Implementation State:	Synthesized
Target Device:	xc6slx16-3csg324	Errors:
Product Version:	ISE 14.7	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Device Utilization Summary (estimated values)				[-]
Logic Utilization	Used	Available	Utilization
Number of Slice Registers	24	18224	0%
Number of Slice LUTs	39	9112	0%
Number of fully used LUT-FF pairs	24	39	61%
Number of bonded IOBs	34	232	14%
Number of BUFG/BUFGCTRLs	1	16	6%

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	週一 四月 18 14:24:33 2016
Translation Report
Map Report
Place and Route Report
CPLD Fitter Report (Text)
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Out of Date	週日 四月 17 22:32:25 2016

Date Generated: 04/18/2016 - 15:08:08