Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) dfb930b1acd743ac8ca2cd659d1b1b76.463AD229AD414389944BD8A3F32627E7.28 Target Package: csg324
Registration ID 211160026_0_0_772 Target Speed: -3
Date Generated 2016-03-17T16:18:15 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 2394 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz CPU Speed 2394 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=3
  • 25-bit adder=1
  • 4-bit adder=2
 Multiplexers=3
  • 15-bit 4-to-1 multiplexer=1
  • 4-bit 2-to-1 multiplexer=2
 RAMs=5
  • 16x15-bit single-port distributed Read Only RAM=4
  • 4x4-bit single-port distributed Read Only RAM=1
 Registers=33
  • Flip-Flops=33
 		MiscellaneousStatistics
  • AGG_BONDED_IO=21
  • AGG_IO=21
  • AGG_LOCED_IO=21
  • AGG_SLICE=19
  • NUM_BONDED_IOB=21
  • NUM_BSFULL=32
  • NUM_BSLUTONLY=19
  • NUM_BSUSED=51
  • NUM_BUFG=1
  • NUM_LOCED_IOB=21
  • NUM_LOGIC_O5ANDO6=5
  • NUM_LOGIC_O5ONLY=23
  • NUM_LOGIC_O6ONLY=22
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=23
  • NUM_SLICEL=14
  • NUM_SLICEX=5
  • NUM_SLICE_CARRY4=7
  • NUM_SLICE_CONTROLSET=3
  • NUM_SLICE_CYINIT=80
  • NUM_SLICE_F7MUX=7
  • NUM_SLICE_FF=33
  • NUM_SLICE_UNUSEDCTRL=9
  • NUM_UNUSABLE_FF_BELS=15
 		NetStatistics
  • NumNets_Active=78
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEIN=11
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=1
  • NumNodesOfType_Active_CLKPIN=10
  • NumNodesOfType_Active_CLKPINFEED=1
  • NumNodesOfType_Active_CNTRLPIN=12
  • NumNodesOfType_Active_DOUBLE=64
  • NumNodesOfType_Active_GENERIC=22
  • NumNodesOfType_Active_GLOBAL=8
  • NumNodesOfType_Active_INPUT=7
  • NumNodesOfType_Active_IOBIN2OUT=20
  • NumNodesOfType_Active_IOBOUTPUT=20
  • NumNodesOfType_Active_LUTINPUT=138
  • NumNodesOfType_Active_OUTBOUND=50
  • NumNodesOfType_Active_OUTPUT=55
  • NumNodesOfType_Active_PADINPUT=19
  • NumNodesOfType_Active_PADOUTPUT=2
  • NumNodesOfType_Active_PINBOUNCE=31
  • NumNodesOfType_Active_PINFEED=178
  • NumNodesOfType_Active_QUAD=22
  • NumNodesOfType_Active_REGINPUT=7
  • NumNodesOfType_Active_SINGLE=85
  • NumNodesOfType_Vcc_HVCCOUT=9
  • NumNodesOfType_Vcc_LUTINPUT=28
  • NumNodesOfType_Vcc_PINFEED=28
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=11
  • IOB-IOBS=10
  • SLICEL-SLICEM=11
  • SLICEX-SLICEL=1
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=7
  • FF_SR=1
  • HARD0=1
  • INVERTER=1
  • IOB=21
  • IOB_IMUX=2
  • IOB_INBUF=2
  • IOB_OUTBUF=19
  • LUT5=28
  • LUT6=51
  • PAD=21
  • REG_SR=32
  • SELMUX2_1=7
  • SLICEL=14
  • SLICEX=5
 
Configuration Data
FF_SR
  • CK=[CK:1] [CK_INV:0]
  • SRINIT=[SRINIT0:1]
  • SYNC_ATTR=[ASYNC:1]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:19]
  • SLEW=[SLOW:19]
  • SUSPEND=[3STATE:19]
 REG_SR
  • CK=[CK:32] [CK_INV:0]
  • LATCH_OR_FF=[FF:32]
  • SRINIT=[SRINIT0:32]
  • SYNC_ATTR=[ASYNC:32]
 SLICEL
  • CLK=[CLK:7] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:3] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=6
  • CO3=6
  • CYINIT=1
  • DI0=6
  • DI1=6
  • DI2=6
  • DI3=6
  • O0=7
  • O1=6
  • O2=6
  • O3=6
  • S0=7
  • S1=6
  • S2=6
  • S3=6
 FF_SR
  • CK=1
  • D=1
  • Q=1
  • SR=1
 HARD0
  • 0=1
 INVERTER
  • IN=1
  • OUT=1
 IOB
  • I=2
  • O=19
  • PAD=21
 IOB_IMUX
  • I=1
  • I_B=1
  • OUT=2
 IOB_INBUF
  • OUT=2
  • PAD=2
 IOB_OUTBUF
  • IN=19
  • OUT=19
 LUT5
  • A2=2
  • A3=1
  • A4=4
  • A5=4
  • O5=28
 LUT6
  • A1=2
  • A2=19
  • A3=21
  • A4=50
  • A5=24
  • A6=49
  • O6=51
 PAD
  • PAD=21
 REG_SR
  • CE=4
  • CK=32
  • D=32
  • Q=32
  • SR=32
 SELMUX2_1
  • 0=7
  • 1=7
  • OUT=7
  • S0=7
 SLICEL
  • A4=7
  • A6=6
  • AQ=7
  • B4=6
  • B6=6
  • BQ=6
  • C2=7
  • C3=7
  • C4=13
  • C5=7
  • C6=13
  • CIN=6
  • CLK=7
  • CMUX=7
  • COUT=6
  • CQ=6
  • CX=7
  • D2=7
  • D3=7
  • D4=13
  • D5=7
  • D6=13
  • DQ=6
  • SR=7
 SLICEX
  • A=2
  • A2=1
  • A3=2
  • A4=5
  • A5=4
  • A6=4
  • AMUX=2
  • AQ=3
  • B=1
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=3
  • BMUX=1
  • BQ=2
  • C=2
  • C1=1
  • C2=1
  • C3=1
  • C4=2
  • C5=2
  • C6=2
  • CE=2
  • CLK=3
  • D1=1
  • D2=2
  • D3=2
  • D4=2
  • D5=2
  • D6=2
  • DMUX=1
  • DQ=2
  • SR=3
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 5 5 0 0 0 0 0
bitgen 7 7 0 0 0 0 0
map 8 8 0 0 0 0 0
ngdbuild 8 8 0 0 0 0 0
par 8 8 0 0 0 0 0
trce 8 8 0 0 0 0 0
xst 69 69 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/upcounterTest PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2016-03-14T16:29:09 PROP_intWbtProjectID=463AD229AD414389944BD8A3F32627E7
PROP_intWbtProjectIteration=28 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.upcounterTest PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=false PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx16 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=5 FILE_VERILOG=12
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=29 NGDBUILD_NUM_FDCE=4 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=24 NGDBUILD_NUM_LUT2=4
NGDBUILD_NUM_LUT3=3 NGDBUILD_NUM_LUT4=3 NGDBUILD_NUM_LUT5=16 NGDBUILD_NUM_LUT6=2
NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_MUXF7=7 NGDBUILD_NUM_OBUF=19 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=25
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=29 NGDBUILD_NUM_FDCE=4 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=24
NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_LUT3=3 NGDBUILD_NUM_LUT4=3 NGDBUILD_NUM_LUT5=16
NGDBUILD_NUM_LUT6=2 NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_MUXF7=7 NGDBUILD_NUM_OBUF=19
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=25
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=358 ms, 27436 KB
Total Signals=31
Total Nets=23
Total Blocks=7
Total Processes=21
Total Simulation Time=1 us
Simulation Resource Usage=0.1092 sec, 1119244 KB
Simulation Mode=gui
Hardware CoSim=0