| cardset Project Status (06/02/2016 - 17:22:47) | |||
| Project File: | Card_Storage.xise | Parser Errors: | No Errors |
| Module Name: | cardset | Implementation State: | Synthesized |
| Target Device: | xc6slx16-3csg324 |
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No Errors |
| Product Version: | ISE 14.7 |
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No Warnings |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice Registers | 59 | 18224 | 0% | |
| Number of Slice LUTs | 100 | 9112 | 1% | |
| Number of fully used LUT-FF pairs | 49 | 110 | 44% | |
| Number of bonded IOBs | 45 | 232 | 19% | |
| Number of BUFG/BUFGCTRLs | 2 | 16 | 12% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 週四 六月 2 17:26:34 2016 | 0 | 0 | 0 | |
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Current | 週四 六月 2 17:30:36 2016 | |