`timescale 1ns / 1ps

module frequency_div(
    output reg clk_out = 1'b0,
    input [25:0] note_div,
    input clk,
    input rst_n
    );
    reg [25:0] q, q_tmp;
    
always@*    
    begin
    if(q == note_div - 1'b1)       
        q_tmp = 26'd0;
    else
        q_tmp = q + 1'b1;
    end
    
always@(posedge clk or negedge rst_n)
    if(~rst_n) q <= 26'd0;
    else 
    begin
        q <= q_tmp;
        if(q == note_div - 1'b1)
            clk_out = ~clk_out;
        else 
            clk_out = clk_out;
    end
endmodule