`timescale 1ns / 1ps

module up_dount_counter(
    output reg [3:0] value,
    output reg carry,
    output reg borrow,
    input clk,
    input [3:0] in_val,
    input rst_n,
    input increase,
    input decrease
    );
    reg [3:0] value_tmp;
    
    always@*
        if(increase)
            if(value == 4'd9)
                begin
                value_tmp = 4'b0000;
                carry = 1'b1;
                borrow = 1'b0;
                end
            else 
                begin
                value_tmp = value + 1'b1;
                carry = 1'b0;
                borrow = 1'b0;
                end
        else if(decrease)
            if(value == 4'd0)
                begin
                value_tmp = 4'd9;
                carry = 1'b0;
                borrow = 1'b1;
                end
            else 
                begin
                value_tmp = value - 1'b1;
                carry = 1'b0;
                borrow = 1'b0;
                end
        else
            begin
            value_tmp = value;
            carry = 1'b0;
            borrow = 1'b0;
            end
            
     always@(posedge clk or negedge rst_n)
        if(~rst_n)
            value <= in_val;
        else
            value <= value_tmp;
            
endmodule