`timescale 1ns / 1ps

module speaker(
    output [7:0] ssd,
    output [3:0] yes,
    output audio_mclk,
    output audio_lrck,
    output audio_sck,
    output audio_sdin,
    input clk,
    input rst_n,
    input increase,
    input decrease,
    input do,
    input re,
    input mi
    );
    wire clk_ctl, clk_d;
    wire [3:0] ssd_in;
    wire [3:0] q1, q0;
    wire carry1, carry0, borrow1, borrow0;
    reg add, minus;
    wire addf, minusf;
    wire [15:0] audio_left, audio_right;
    reg [21:0] note;
    reg [15:0] sound;
    
    
    always@*
        if(q1 == 4'd0 && q0 == 4'd1)
            begin
            add = addf; 
            minus = 0;
            end
        else if(q1 == 4'd1 && q0 == 4'd6)
            begin
            add = 0; 
            minus = minusf;
            end
        else
            begin
            add = addf; 
            minus = minusf;
            end
    always@*
        if(do)
            note = 22'd191571;
        else if(re)
            note = 22'd170648;
        else if(mi)
            note = 22'd151515;
        else 
            note = 22'd0;
    always@*
        sound = 4'd10 * q1 + q0;
         
    speaker_control U_speaker_control(
      .audio_mclk(audio_mclk),
      .audio_lrck(audio_lrck),
      .audio_sck(audio_sck),
      .audio_sdin(audio_sdin),
      .clk(clk),
      .rst_n(rst_n),
      .audio_left(audio_left),
      .audio_right(audio_right)
    );
    note_frequency U_note(
      .audio_left(audio_left),
      .audio_right(audio_right),
      .note_div(note),
      .clk(clk),
      .rst_n(rst_n),
      .sound(sound)
    );    
    up_dount_counter U_counter1(
      .value(q1),
      .carry(carry1),
      .borrow(borrow1),
      .clk(clk),
      .in_val(4'd0),
      .rst_n(rst_n),
      .increase(carry0),
      .decrease(borrow0)
    );
    up_dount_counter U_counter0(
      .value(q0),
      .carry(carry0),
      .borrow(borrow0),
      .clk(clk),
      .in_val(4'd1),
      .rst_n(rst_n),
      .increase(add),
      .decrease(minus)
    );
    frectl U_FD(
    .clk_out(clk_d),
    .ctl(clk_ctl),
    .clk(clk),
    .rst_n(rst_n)
   );
   scan_2 U_SC(
    .ssd_ctl(yes),
    .ssd_in(ssd_in),
    .in0(q1),
    .in1(q0),
    .ssd_ctl_en(clk_ctl) 
   );
   display_n U_D(
    .i(ssd_in),
    .SSD(ssd)
    );
    one_pulse U_add(
      .out_pulse(addf),
      .clk(clk),
      .rst_n(rst_n),
      .in_trig(increase)
    );
    one_pulse U_minus(
      .out_pulse(minusf),
      .clk(clk),
      .rst_n(rst_n),
      .in_trig(decrease)
    );
    
endmodule