`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/20 16:49:12
// Design Name: 
// Module Name: display1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


`define SS_0 8'b00000011
`define SS_1 8'b10011111
`define SS_2 8'b00100101
`define SS_3 8'b00001101
`define SS_4 8'b10011001
`define SS_5 8'b01001001
`define SS_6 8'b01000001
`define SS_7 8'b00011111
`define SS_8 8'b00000001
`define SS_9 8'b00001001

module display_n(
    input [3:0] i,
    output reg [7:0] SSD
    );

always@*
  case (i)
    4'd0: SSD = `SS_0;
    4'd1: SSD = `SS_1;
    4'd2: SSD = `SS_2;
    4'd3: SSD = `SS_3;
    4'd4: SSD = `SS_4;
    4'd5: SSD = `SS_5;
    4'd6: SSD = `SS_6;
    4'd7: SSD = `SS_7;
    4'd8: SSD = `SS_8;
    4'd9: SSD = `SS_9;
    default: SSD = 8'b11111111;
  endcase
     
endmodule