`timescale 1ns / 1ps

module up_count(
    output reg [4:0] value,
    input clk,
    input [4:0] limit,
    input rst_n,
    input increase
    );
    reg [4:0] value_tmp;
    
    always@*
        if(value == limit && increase)
            value_tmp = 5'd0;
        else if(increase)
            value_tmp = value + 5'd1;
        else
            value_tmp = value;
            
     always@(negedge rst_n or negedge clk)
        if(~rst_n)
            value <= 5'd0;
        else
            value <= value_tmp;
            
endmodule