`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/04/25 13:30:13
// Design Name: 
// Module Name: test_speaker
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module test_speaker();
    reg [15:0] audio_left;
    reg [15:0] audio_right;
    wire audio_mclk;
    wire audio_lrck;
    reg rst_n;
    wire audio_sck;
    wire audio_sdin;
    reg clk;
    
speaker_control U_speaker_control(
      .audio_mclk(audio_mclk),
      .audio_lrck(audio_lrck),
      .audio_sck(audio_sck),
      .audio_sdin(audio_sdin),
      .clk(clk),
      .rst_n(rst_n),
      .audio_left(audio_left),
      .audio_right(audio_right)
    );
   
    initial begin
    audio_left = 16'b1011_0111_0101_1001;
    audio_right = 16'b1111_1001_0010_0010;
    rst_n = 0;clk = 0;
    #0.1 rst_n = 1;
    end
    
    always
        begin
        #0.05 clk = ~clk;
        end
endmodule