`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/28 00:44:47
// Design Name: 
// Module Name: test_prelab5
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module test_prelab5();
    reg clk, rst_n, stop;
    wire state;
    pre_lab5_1 U0(
        .clk(clk),
        .rst_n(rst_n),
        .stop(stop),
        .state(state)
    );   
    initial
    begin
    clk = 0; rst_n = 0; stop = 0;
    #1 stop = 1;
    #1 rst_n = 1;
    #20 stop = 0;
    
    end
    always #1 clk = ~clk;
    always #10 stop = ~stop;
endmodule