`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/28 16:31:08
// Design Name: 
// Module Name: up_count
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module up_count(
    output reg [3:0] value,
    output reg carry,
    input clk,
    input [3:0] limit,
    input rst_n,
    input increase
    );
    reg [3:0] value_tmp;
    
    always@*
        if(value == limit && increase)
            begin
            value_tmp = 4'b0000;
            carry = 1'b1;
            end
        else if(increase)
            begin
            value_tmp = value + 1'b1;
            carry = 0;
            end
        else
            begin
            value_tmp = value;
            carry = 0;
            end
            
     always@(posedge clk or negedge rst_n)
        if(~rst_n)
            value <= 4'd0;
        else
            value <= value_tmp;
            
endmodule