`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/04/03 10:32:10
// Design Name: 
// Module Name: time
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module time_clk(
    output [3:0] m1,
    output [3:0] m0,
    output [3:0] s1,
    output [3:0] s0,
    input [3:0] set_m1,
    input [3:0] set_m0,
    input [3:0] set_s1,
    input [3:0] set_s0,
    input clk,
    input rst_n,
    input count_enable
    );
    wire bow1, bow2, bow3, bow4;
    
    down_count U_m1(
        .value(m1),
        .borrow(bow4),
        .clk(clk),
        .limit(4'd5),
        .set(set_m1),
        .rst_n(rst_n),
        .decrease(bow3)
    );
    down_count U_m0(
        .value(m0),
        .borrow(bow3),
        .clk(clk),
        .limit(4'd9),
        .set(set_m0),
        .rst_n(rst_n),
        .decrease(bow2)
    );
    down_count U_s1(
        .value(s1),
        .borrow(bow2),
        .clk(clk),
        .limit(4'd5),
        .set(set_s1),
        .rst_n(rst_n),
        .decrease(bow1)
    );
    down_count U_s0(
        .value(s0),
        .borrow(bow1),
        .clk(clk),
        .limit(4'd9),
        .set(set_s0),
        .rst_n(rst_n),
        .decrease(count_enable)
    );
endmodule