`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/14 18:43:59
// Design Name: 
// Module Name: scan_ctl
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module scan_ctl(
    output reg [3:0] ssd_ctl,
    output reg [3:0] ssd_in,
    input [3:0] in0,
    input [3:0] in1,
    input [3:0] in2,
    input [3:0] in3,
    input [1:0] ssd_ctl_en
    );
    
    always@*
        case(ssd_ctl_en)
        2'b00:
            begin
            ssd_ctl = 4'b0111;
            ssd_in = in0;
            end
        2'b01:
            begin
            ssd_ctl = 4'b1011;
            ssd_in = in1;
            end
        2'b10:
            begin
            ssd_ctl = 4'b1101;
            ssd_in = in2;
            end
        default:
            begin
            ssd_ctl = 4'b1110;
            ssd_in = in3;
            end    
        endcase

        
endmodule