`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/24 10:59:26
// Design Name: 
// Module Name: one_pulse
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module one_pulse(
    output reg out_pulse,
    input clk,
    input rst_n,
    input in_trig
    );
    reg in_trig_delay;
    wire out_pulse_next;
    
    always@(posedge clk or negedge rst_n)
        if(~rst_n) in_trig_delay <= 1'b0;
        else in_trig_delay <= in_trig;
        
    assign out_pulse_next = in_trig & (~in_trig_delay);
    
    always@(posedge clk or negedge rst_n)
        if(~rst_n) out_pulse <= 1'b0;
        else out_pulse <= out_pulse_next;
        
endmodule