`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/25 15:47:21
// Design Name: 
// Module Name: fsm
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module fsm(
    output reg count_enable,
    output reg set_enable,
    input clk,
    input rst_n,
    input in,
    input mode
    );
    reg [1:0] state;
    reg [1:0] next_state;
    
    always@*
        case(state)
            2'b00:
              if(in)
                begin
                next_state = 2'b01;
                set_enable = 0;
                count_enable = 1;
                end
              else if(mode)
                begin
                next_state = 2'b10;
                set_enable = 1;
                count_enable = 0;
                end
              else
                begin
                next_state = 2'b00;
                set_enable = 0;
                count_enable = 0;
                end
            2'b01:
              if(in)
                begin
                next_state = 2'b00;
                set_enable = 0;
                count_enable = 0;
                end
              else if(mode)
                begin
                next_state = 2'b10;
                set_enable = 1;
                count_enable = 0;
                end
              else
                begin
                next_state = 2'b01;
                set_enable = 0;
                count_enable = 1;
                end
            2'b10:
              if(mode)
                begin
                next_state = 2'b10;
                set_enable = 1;
                count_enable = 0;
                end
              else
                begin
                next_state = 2'b00;
                set_enable = 0;
                count_enable = 0;
                end
            default:
                begin
                next_state = 2'b01;
                set_enable = 0;
                count_enable = 1;
                end
            endcase
            
    always@(posedge clk or negedge rst_n)
        if(~rst_n) state <= 2'b00;
        else state <= next_state;
        
endmodule