`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/28 16:18:47
// Design Name: 
// Module Name: freqdiv_ctl2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module freqdiv_ctl2(
    output reg clk_out,
    output reg [1:0] ctl,
    input clk,
    input rst_n
    );
    reg [25:0] q, q_tmp;
    
always@*    
    begin
    ctl = {q[17], q[16]};
    if(q == 26'd50000000 - 1'b1)       
        q_tmp = 26'd0;
    else
        q_tmp = q + 1'b1;
    end
    
always@(posedge clk or negedge rst_n)
    if(~rst_n) q <= 26'd0;
    else 
    begin
        q <= q_tmp;
        if(q == 26'd50000000 - 1'b1)
            clk_out = ~clk_out;
        else 
            clk_out = clk_out;
    end

endmodule