Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------
| Tool Version     : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
| Date             : Tue Feb 02 17:06:55 2016
| Host             : WK84 running 64-bit major release  (build 9200)
| Command          : 
| Design           : Servo_interface
| Device           : xc7a35tcpg236-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
----------------------------------------------------------------------------------------

Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+-------+
| Total On-Chip Power (W)  | 1.604 |
| Dynamic (W)              | 1.528 |
| Device Static (W)        | 0.075 |
| Effective TJA (C/W)      | 5.0   |
| Max Ambient (C)          | 77.0  |
| Junction Temperature (C) | 33.0  |
| Confidence Level         | Low   |
| Setting File             | ---   |
| Simulation Activity File | ---   |
| Design Nets Matched      | NA    |
+--------------------------+-------+


1.1 On-Chip Components
----------------------

+----------------+-----------+----------+-----------+-----------------+
| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic    |     0.159 |       87 |       --- |             --- |
|   LUT as Logic |     0.132 |       38 |     20800 |            0.18 |
|   CARRY4       |     0.015 |        8 |      8150 |            0.10 |
|   Register     |     0.007 |       20 |     41600 |            0.05 |
|   BUFG         |     0.006 |        1 |        32 |            3.13 |
|   Others       |     0.000 |        5 |       --- |             --- |
| Signals        |     0.253 |       98 |       --- |             --- |
| DSPs           |     0.001 |        1 |        90 |            1.11 |
| I/O            |     1.115 |       19 |       106 |           17.92 |
| Static Power   |     0.075 |          |           |                 |
| Total          |     1.604 |          |           |                 |
+----------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     0.498 |       0.485 |      0.013 |
| Vccaux    |       1.800 |     0.051 |       0.038 |      0.013 |
| Vcco33    |       3.300 |     0.296 |       0.295 |      0.001 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                             |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                                    |
| Clock nodes activity        | Low        | User specified less than 75% of clocks                 | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views         |
| Device models               | High       | Device models are Production                           |                                                                                                                    |
|                             |            |                                                        |                                                                                                                    |
| Overall confidence level    | Low        |                                                        |                                                                                                                    |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 5.0                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 4.6                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+-----------------+-----------+
| Name            | Power (W) |
+-----------------+-----------+
| Servo_interface |     1.528 |
|   count         |     0.115 |
|   decode        |     0.128 |
+-----------------+-----------+


