Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
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| Tool Version      : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
| Date              : Tue Feb 02 17:06:56 2016
| Host              : WK84 running 64-bit major release  (build 9200)
| Command           : report_clock_utilization -file Servo_interface_clock_utilization_routed.rpt
| Design            : Servo_interface
| Device            : 7a35t-cpg236
| Speed File        : -1  PRODUCTION 1.14 2014-09-11
| Temperature Grade : C
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Clock Utilization Report

Table of Contents
-----------------
1. Clock Primitive Utilization
2. Details of Global Clocks
3. Details of Regional Clocks
4. Details of Multi-Regional Clocks
5. Details of I/O Clocks
6. Details of Local Clocks
7. Clock Regions : Key Resource Utilization
8. Net wise resources used in clock region X0Y0

1. Clock Primitive Utilization
------------------------------

+-------+------+-----------+-----------+
| Type  | Used | Available | Num Fixed |
+-------+------+-----------+-----------+
| BUFG  |    1 |        32 |         0 |
| BUFH  |    0 |        72 |         0 |
| BUFIO |    0 |        20 |         0 |
| MMCM  |    0 |         5 |         0 |
| PLL   |    0 |         5 |         0 |
| BUFR  |    0 |        20 |         0 |
| BUFMR |    0 |        10 |         0 |
+-------+------+-----------+-----------+


2. Details of Global Clocks
---------------------------

+-------+--------------------+---------------+--------------+-------+
|       |                    |               |   Num Loads  |       |
+-------+--------------------+---------------+------+-------+-------+
| Index | BUFG Cell          | Net Name      | BELs | Sites | Fixed |
+-------+--------------------+---------------+------+-------+-------+
|     1 | clk_IBUF_BUFG_inst | clk_IBUF_BUFG |   20 |     5 |    no |
+-------+--------------------+---------------+------+-------+-------+


3. Details of Regional Clocks
-----------------------------

4. Details of Multi-Regional Clocks
-----------------------------------

5. Details of I/O Clocks
------------------------

6. Details of Local Clocks
--------------------------

7. Clock Regions : Key Resource Utilization
-------------------------------------------

+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E1   |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   20 |  9600 |    0 |  1600 |    0 |    20 |    0 |    10 |    1 |    20 |
| X1Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 12000 |    0 |  1800 |    0 |    40 |    0 |    20 |    0 |    20 |
| X0Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  9600 |    0 |  1600 |    0 |    20 |    0 |    10 |    0 |    20 |
| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 12000 |    0 |  1800 |    0 |    40 |    0 |    20 |    0 |    20 |
| X0Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 14400 |    0 |  1600 |    0 |    20 |    0 |    10 |    0 |    20 |
| X1Y2              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     5 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |  7600 |    0 |  1200 |    0 |    10 |    0 |     5 |    0 |    20 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* RAMB36 site can be used as two RAMB18/FIFO18 sites.


8. Net wise resources used in clock region X0Y0
-----------------------------------------------

+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+
| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | Clock Net Name |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+
| BUFG        | BUFHCE_X0Y8 |   no  |         0 |        0 |       0 |         0 |       0 |       0 |  20 |     0 |        0 | clk_IBUF_BUFG  |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+



# Location of BUFG Primitives 
set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]

# Location of IO Clock Primitives

# Location of MMCM Clock Primitives

# Location of BUFH Clock Primitives

# Location of BUFR Clock Primitives

# Location of BUFMR Clock Primitives

# Location of PLL Clock Primitives

# Location of IO Primitives which is load of clock spine

# Location of clock ports
set_property LOC IOB_X1Y26 [get_ports clk]

# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_clk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks  {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}
#endgroup
