Index of /archive/邏設實驗/110李濬屹/Lab 2/
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Visio/ 23-Oct-2024 06:04 -
1-1.png 23-Oct-2024 06:04 27K
FPGA_1.png 23-Oct-2024 06:04 111K
FPGA_2.png 23-Oct-2024 06:04 7667
Lab-2-Advanced-Gate-Level-Verilog.pdf 23-Oct-2024 06:04 2M
Lab2_Team30_Carry_Look_Ahead_Adder_8bit.v 23-Oct-2024 06:04 3269
Lab2_Team30_Carry_Look_Ahead_Adder_8bit_t.v 23-Oct-2024 06:04 1183
Lab2_Team30_Decode_And_Execute_4bit.v 23-Oct-2024 06:04 5767
Lab2_Team30_Decode_And_Execute_4bit_fpga.v 23-Oct-2024 06:04 1834
Lab2_Team30_Decode_And_Execute_t.v 23-Oct-2024 06:04 485
Lab2_Team30_Exhausted_Testing.v 23-Oct-2024 06:04 1317
Lab2_Team30_Multiplier_4bit.v 23-Oct-2024 06:04 3507
Lab2_Team30_Multiplier_4bit_t.v 23-Oct-2024 06:04 973
Lab2_Team30_Report.docx 23-Oct-2024 06:04 6M
Lab2_Team30_Report.pdf 23-Oct-2024 06:04 2M
Lab2_Team30_Ripple_Carry_Adder.v 23-Oct-2024 06:04 3063
Lab2_Team30_Ripple_Carry_Adder_t.v 23-Oct-2024 06:04 523
Q1_gates.png 23-Oct-2024 06:04 31K
Q1_nand_implement.png 23-Oct-2024 06:04 74K
Q1_ripple_carry_adder.png 23-Oct-2024 06:04 28K
Q2_4bit8x1mux.png 23-Oct-2024 06:04 61K
Q2_8bitor_all.png 23-Oct-2024 06:04 55K
Q2_ADD_SUB_BITWISEAND_BITWISEOR.png 23-Oct-2024 06:04 37K
Q2_buffer_XNOR_NOR_HA_FA.png 23-Oct-2024 06:04 30K
Q2_compare.png 23-Oct-2024 06:04 27K
Q2_comparegt_eq_4bitand.png 23-Oct-2024 06:04 33K
Q2_ls_rs.png 23-Oct-2024 06:04 24K
Q2_not_and_or_xor.png 23-Oct-2024 06:04 30K
Q2_universal_gate.png 23-Oct-2024 06:04 4504
~$b2_Team30_Report.docx 23-Oct-2024 06:04 162