Index of /archive/邏設實驗/108黃元豪/miscellaneous/

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01_Syllabus.pdf                                    23-Oct-2024 06:04    228K
01_Verilog_I.pdf                                   23-Oct-2024 06:04      5M
01_Verilog_II.pdf                                  23-Oct-2024 06:04      2M
02_FPGA_Emulation.pdf                              23-Oct-2024 06:04      7M
03_Counter.pdf                                     23-Oct-2024 06:04      3M
04_shifter.pdf                                     23-Oct-2024 06:04      1M
05_Finite_State_Machine.pdf                        23-Oct-2024 06:04      4M
06_Clock_Display.pdf                               23-Oct-2024 06:04    175K
07_Clock_Multifunction.pdf                         23-Oct-2024 06:04    380K
Basys3_rm.pdf                                      23-Oct-2024 06:04    741K
CummingsHDLCON2002_Parameters.pdf                  23-Oct-2024 06:04     81K
FPGA PROTOTYPING BY VERILOG EXAMPLES .pdf          23-Oct-2024 06:04     19M
FPGA Prototyping with Verilog examples.pdf         23-Oct-2024 06:04     22M
FPGAPrototypingByVerilogExamples.pdf               23-Oct-2024 06:04     21M
Lab-0.2-Vivado-Simulation.pdf                      23-Oct-2024 06:04      2M
Lab-0.3-Vivado-Basys3-Implementation.pdf           23-Oct-2024 06:04      5M
Lab02_FPGAEmulation.pdf                            23-Oct-2024 06:04     76K
Lab07_Electronic_Clock.pdf                         23-Oct-2024 06:04     53K
fulladder.txt                                      23-Oct-2024 06:04     589
題目.pdf                                             23-Oct-2024 06:04     56K