Index of /archive/邏設實驗/108黃元豪/final project/old/

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lab11_VGA_source/                                  23-Oct-2024 06:04       -
08_Speaker.pdf                                     23-Oct-2024 06:04    659K
09_Keyboard.pdf                                    23-Oct-2024 06:04    927K
10_Electronic_Organ.pdf                            23-Oct-2024 06:04    278K
11_VGA.pdf                                         23-Oct-2024 06:04      2M
12_random_number_generator.pdf                     23-Oct-2024 06:04    566K
FF_final_project.pdf                               23-Oct-2024 06:04    243K
Final Project Proposal .doc                        23-Oct-2024 06:04     60K
Final-Project-Proposal.doc                         23-Oct-2024 06:04     60K
For Loop - VHDL _ Verilog Example.pdf              23-Oct-2024 06:04    112K
Project Examples.pdf                               23-Oct-2024 06:04    128K
Specification.txt                                  23-Oct-2024 06:04     525
final_project_TOP.v                                23-Oct-2024 06:04     27K
一些常見io定義.txt                                       23-Oct-2024 06:04     12K