reg [15:0] timer;
  
  always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
      timer <= 'b0;
    end else if (raw == debounced) begin
      timer <= 16'b0;
    end else begin
      timer <= timer + 16'b1;
    end
  end
  
  always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
      debounced <= 'b0;
    end else if (timer == 16'hFFFF) begin
      debounced <= raw;
    end else begin
      debounced <= debounced;
    end
  end