Index of /archive/邏設實驗/107馬席彬/Lab_zip/lab11_3_107061212_ver1.zip (Unzipped Files)/

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blk_mem_gen_0/                                     23-Oct-2024 06:04       -
blk_mem_gen_1/                                     23-Oct-2024 06:04       -
blk_mem_gen_2/                                     23-Oct-2024 06:04       -
blk_mem_gen_3/                                     23-Oct-2024 06:04       -
blk_mem_gen_4/                                     23-Oct-2024 06:04       -
blk_mem_gen_5/                                     23-Oct-2024 06:04       -
blk_mem_gen_6/                                     23-Oct-2024 06:04       -
1.JPG                                              23-Oct-2024 06:04    9956
2.JPG                                              23-Oct-2024 06:04     10K
3.JPG                                              23-Oct-2024 06:04     10K
4.JPG                                              23-Oct-2024 06:04    9678
5.JPG                                              23-Oct-2024 06:04     10K
6.JPG                                              23-Oct-2024 06:04     11K
7.JPG                                              23-Oct-2024 06:04     10K
clock_divisor.v                                    23-Oct-2024 06:04     270
clock_generator.v                                  23-Oct-2024 06:04    2621
lab11_3.xdc                                        23-Oct-2024 06:04    1758
mem_addr_gen.v                                     23-Oct-2024 06:04     687
random.v                                           23-Oct-2024 06:04    1282
topmodule.bit                                      23-Oct-2024 06:04      2M
topmodule.v                                        23-Oct-2024 06:04    5071
vga_controller.v                                   23-Oct-2024 06:04    2174