Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) d96cc176c19a412192bec84ffaf3406b.4F60E1A4648D401286AAB295B69C7DEF.1 Target Package: csg324
Registration ID 210913348_0_0_143 Target Speed: -3
Date Generated 2015-04-17T02:09:02 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz CPU Speed 2494 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz CPU Speed 2494 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=2
  • 25-bit adder=1
  • 4-bit adder=1
 Counters=1
  • 2-bit up counter=1
 Multiplexers=5
  • 1-bit 2-to-1 multiplexer=2
  • 4-bit 2-to-1 multiplexer=3
 RAMs=3
  • 16x15-bit single-port distributed Read Only RAM=1
  • 4x4-bit single-port distributed Read Only RAM=2
 Registers=35
  • Flip-Flops=35
 		MiscellaneousStatistics
  • AGG_BONDED_IO=38
  • AGG_IO=38
  • AGG_LOCED_IO=38
  • AGG_SLICE=21
  • NUM_BONDED_IOB=38
  • NUM_BSFULL=28
  • NUM_BSLUTONLY=21
  • NUM_BSUSED=49
  • NUM_BUFG=1
  • NUM_LOCED_IOB=38
  • NUM_LOGIC_O5ANDO6=9
  • NUM_LOGIC_O5ONLY=16
  • NUM_LOGIC_O6ONLY=23
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=16
  • NUM_SLICEL=5
  • NUM_SLICEX=16
  • NUM_SLICE_CARRY4=5
  • NUM_SLICE_CONTROLSET=3
  • NUM_SLICE_CYINIT=75
  • NUM_SLICE_FF=30
  • NUM_SLICE_UNUSEDCTRL=11
  • NUM_UNUSABLE_FF_BELS=10
 		NetStatistics
  • NumNets_Active=106
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEIN=7
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=2
  • NumNodesOfType_Active_CLKPIN=10
  • NumNodesOfType_Active_CLKPINFEED=2
  • NumNodesOfType_Active_CNTRLPIN=12
  • NumNodesOfType_Active_DOUBLE=60
  • NumNodesOfType_Active_GENERIC=38
  • NumNodesOfType_Active_GLOBAL=10
  • NumNodesOfType_Active_INPUT=5
  • NumNodesOfType_Active_IOBIN2OUT=32
  • NumNodesOfType_Active_IOBOUTPUT=32
  • NumNodesOfType_Active_LUTINPUT=165
  • NumNodesOfType_Active_OUTBOUND=68
  • NumNodesOfType_Active_OUTPUT=65
  • NumNodesOfType_Active_PADINPUT=27
  • NumNodesOfType_Active_PADOUTPUT=6
  • NumNodesOfType_Active_PINBOUNCE=30
  • NumNodesOfType_Active_PINFEED=213
  • NumNodesOfType_Active_QUAD=60
  • NumNodesOfType_Active_SINGLE=97
  • NumNodesOfType_Vcc_GENERIC=5
  • NumNodesOfType_Vcc_HVCCOUT=16
  • NumNodesOfType_Vcc_IOBIN2OUT=5
  • NumNodesOfType_Vcc_IOBOUTPUT=5
  • NumNodesOfType_Vcc_LUTINPUT=25
  • NumNodesOfType_Vcc_PADINPUT=5
  • NumNodesOfType_Vcc_PINFEED=30
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=21
  • IOB-IOBS=17
  • SLICEX-SLICEL=9
  • SLICEX-SLICEM=2
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=5
  • FF_SR=2
  • HARD0=1
  • INVERTER=5
  • IOB=38
  • IOB_IMUX=6
  • IOB_INBUF=6
  • IOB_OUTBUF=32
  • LUT5=25
  • LUT6=49
  • PAD=38
  • REG_SR=28
  • SLICEL=5
  • SLICEX=16
 
Configuration Data
FF_SR
  • CK=[CK:2] [CK_INV:0]
  • SRINIT=[SRINIT0:2]
  • SYNC_ATTR=[ASYNC:2]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:32]
  • SLEW=[SLOW:32]
  • SUSPEND=[3STATE:32]
 REG_SR
  • CK=[CK:28] [CK_INV:0]
  • LATCH_OR_FF=[FF:28]
  • SRINIT=[SRINIT0:28]
  • SYNC_ATTR=[ASYNC:28]
 SLICEL
  • CLK=[CLK:5] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:5] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=4
  • CO3=4
  • CYINIT=1
  • DI0=5
  • DI1=4
  • DI2=4
  • DI3=4
  • O0=5
  • O1=5
  • O2=4
  • O3=4
  • S0=5
  • S1=5
  • S2=4
  • S3=4
 FF_SR
  • CK=2
  • D=2
  • Q=2
  • SR=2
 HARD0
  • 0=1
 INVERTER
  • IN=5
  • OUT=5
 IOB
  • I=6
  • O=32
  • PAD=38
 IOB_IMUX
  • I=1
  • I_B=5
  • OUT=6
 IOB_INBUF
  • OUT=6
  • PAD=6
 IOB_OUTBUF
  • IN=32
  • OUT=32
 LUT5
  • A1=1
  • A2=1
  • A3=2
  • A4=6
  • A5=8
  • O5=25
 LUT6
  • A1=21
  • A2=21
  • A3=23
  • A4=49
  • A5=29
  • A6=47
  • O6=49
 PAD
  • PAD=38
 REG_SR
  • CE=4
  • CK=28
  • D=28
  • Q=28
  • SR=28
 SLICEL
  • A4=5
  • A6=5
  • AQ=5
  • B4=5
  • B6=4
  • BQ=5
  • C4=4
  • C6=4
  • CIN=4
  • CLK=5
  • COUT=4
  • CQ=4
  • D4=4
  • D6=4
  • DQ=4
  • SR=5
 SLICEX
  • A=10
  • A1=7
  • A2=7
  • A3=8
  • A4=14
  • A5=13
  • A6=13
  • AMUX=6
  • AQ=4
  • B=2
  • B1=3
  • B2=3
  • B3=3
  • B4=4
  • B5=3
  • B6=4
  • BMUX=1
  • BQ=2
  • C1=4
  • C2=4
  • C3=4
  • C4=4
  • C5=4
  • C6=4
  • CE=2
  • CLK=5
  • CQ=4
  • D=9
  • D1=7
  • D2=7
  • D3=8
  • D4=9
  • D5=9
  • D6=9
  • DMUX=1
  • SR=5
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 248 243 0 0 0 0 0
bitgen 217 217 0 0 0 0 0
map 215 215 0 0 0 0 0
netgen 1 1 0 0 0 0 0
ngc2edif 2 2 0 0 0 0 0
ngdbuild 228 228 0 0 0 0 0
par 214 214 0 0 0 0 0
trce 214 214 0 0 0 0 0
xps 2 0 0 0 0 0 0
xst 326 317 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/spartan6/libs_le_acc16.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2015-04-17T02:03:18
PROP_intWbtProjectID=4F60E1A4648D401286AAB295B69C7DEF PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx16 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=5
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=26 NGDBUILD_NUM_FDCE=4 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=5 NGDBUILD_NUM_INV=7 NGDBUILD_NUM_LUT1=17 NGDBUILD_NUM_LUT2=14
NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT4=2 NGDBUILD_NUM_LUT5=1 NGDBUILD_NUM_LUT6=20
NGDBUILD_NUM_MUXCY=17 NGDBUILD_NUM_OBUF=32 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=18
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=26 NGDBUILD_NUM_FDCE=4 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=5 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=7 NGDBUILD_NUM_LUT1=17
NGDBUILD_NUM_LUT2=14 NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT4=2 NGDBUILD_NUM_LUT5=1
NGDBUILD_NUM_LUT6=20 NGDBUILD_NUM_MUXCY=17 NGDBUILD_NUM_OBUF=32 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=18
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5