Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) d96cc176c19a412192bec84ffaf3406b.F2F6E1184DFF449EA3C2570EA74F7386.7 Target Package: csg324
Registration ID 210913348_0_0_143 Target Speed: -3
Date Generated 2015-04-08T02:38:01 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz CPU Speed 2494 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz CPU Speed 2494 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=3
  • 25-bit adder=1
  • 4-bit subtractor=2
 Multiplexers=8
  • 1-bit 2-to-1 multiplexer=1
  • 4-bit 2-to-1 multiplexer=6
  • 4-bit 3-to-1 multiplexer=1
 RAMs=2
  • 16x15-bit single-port distributed Read Only RAM=1
  • 4x4-bit single-port distributed Read Only RAM=1
 Registers=34
  • Flip-Flops=34
 		MiscellaneousStatistics
  • AGG_BONDED_IO=38
  • AGG_IO=38
  • AGG_LOCED_IO=38
  • AGG_SLICE=22
  • NUM_BONDED_IOB=38
  • NUM_BSFULL=33
  • NUM_BSLUTONLY=25
  • NUM_BSUSED=58
  • NUM_BUFG=1
  • NUM_LOCED_IOB=38
  • NUM_LOGIC_O5ANDO6=5
  • NUM_LOGIC_O5ONLY=23
  • NUM_LOGIC_O6ONLY=29
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=23
  • NUM_SLICEL=9
  • NUM_SLICEX=13
  • NUM_SLICE_CARRY4=7
  • NUM_SLICE_CONTROLSET=2
  • NUM_SLICE_CYINIT=87
  • NUM_SLICE_F7MUX=2
  • NUM_SLICE_FF=33
  • NUM_SLICE_UNUSEDCTRL=11
  • NUM_UNUSABLE_FF_BELS=7
 		NetStatistics
  • NumNets_Active=109
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=1
  • NumNodesOfType_Active_BOUNCEIN=13
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=2
  • NumNodesOfType_Active_CLKPIN=11
  • NumNodesOfType_Active_CLKPINFEED=2
  • NumNodesOfType_Active_CNTRLPIN=11
  • NumNodesOfType_Active_DOUBLE=63
  • NumNodesOfType_Active_GENERIC=35
  • NumNodesOfType_Active_GLOBAL=10
  • NumNodesOfType_Active_INPUT=7
  • NumNodesOfType_Active_IOBIN2OUT=32
  • NumNodesOfType_Active_IOBOUTPUT=32
  • NumNodesOfType_Active_LUTINPUT=192
  • NumNodesOfType_Active_OUTBOUND=67
  • NumNodesOfType_Active_OUTPUT=71
  • NumNodesOfType_Active_PADINPUT=30
  • NumNodesOfType_Active_PADOUTPUT=3
  • NumNodesOfType_Active_PINBOUNCE=24
  • NumNodesOfType_Active_PINFEED=245
  • NumNodesOfType_Active_QUAD=48
  • NumNodesOfType_Active_REGINPUT=2
  • NumNodesOfType_Active_SINGLE=105
  • NumNodesOfType_Vcc_GENERIC=5
  • NumNodesOfType_Vcc_HVCCOUT=15
  • NumNodesOfType_Vcc_IOBIN2OUT=5
  • NumNodesOfType_Vcc_IOBOUTPUT=5
  • NumNodesOfType_Vcc_LUTINPUT=28
  • NumNodesOfType_Vcc_PADINPUT=5
  • NumNodesOfType_Vcc_PINFEED=33
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=20
  • IOB-IOBS=18
  • SLICEL-SLICEM=8
  • SLICEX-SLICEL=4
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=7
  • HARD0=1
  • INVERTER=1
  • IOB=38
  • IOB_IMUX=3
  • IOB_INBUF=3
  • IOB_OUTBUF=35
  • LUT5=28
  • LUT6=58
  • PAD=38
  • REG_SR=33
  • SELMUX2_1=2
  • SLICEL=9
  • SLICEX=13
 
Configuration Data
IOB_OUTBUF
  • DRIVEATTRBOX=[12:35]
  • SLEW=[SLOW:35]
  • SUSPEND=[3STATE:35]
 REG_SR
  • CK=[CK:33] [CK_INV:0]
  • LATCH_OR_FF=[FF:33]
  • SRINIT=[SRINIT0:31] [SRINIT1:2]
  • SYNC_ATTR=[ASYNC:33]
 SLICEL
  • CLK=[CLK:9] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:2] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=6
  • CO3=6
  • CYINIT=1
  • DI0=6
  • DI1=6
  • DI2=6
  • DI3=6
  • O0=7
  • O1=6
  • O2=6
  • O3=6
  • S0=7
  • S1=6
  • S2=6
  • S3=6
 HARD0
  • 0=1
 INVERTER
  • IN=1
  • OUT=1
 IOB
  • I=3
  • O=35
  • PAD=38
 IOB_IMUX
  • I=2
  • I_B=1
  • OUT=3
 IOB_INBUF
  • OUT=3
  • PAD=3
 IOB_OUTBUF
  • IN=35
  • OUT=35
 LUT5
  • A1=1
  • A2=2
  • A3=2
  • A4=4
  • A5=4
  • O5=28
 LUT6
  • A1=21
  • A2=22
  • A3=26
  • A4=56
  • A5=33
  • A6=57
  • O6=58
 PAD
  • PAD=38
 REG_SR
  • CK=33
  • D=33
  • Q=33
  • SR=33
 SELMUX2_1
  • 0=2
  • 1=2
  • OUT=2
  • S0=2
 SLICEL
  • A1=2
  • A2=2
  • A3=2
  • A4=9
  • A5=2
  • A6=8
  • AQ=9
  • B=2
  • B2=1
  • B3=1
  • B4=7
  • B5=2
  • B6=8
  • BMUX=1
  • BQ=7
  • C2=1
  • C3=2
  • C4=8
  • C5=2
  • C6=8
  • CIN=6
  • CLK=9
  • COUT=6
  • CQ=8
  • CX=2
  • D1=2
  • D2=2
  • D3=2
  • D4=8
  • D5=2
  • D6=8
  • DQ=6
  • SR=9
 SLICEX
  • A=7
  • A1=7
  • A2=7
  • A3=7
  • A4=9
  • A5=9
  • A6=9
  • AMUX=2
  • AQ=2
  • B=5
  • B1=4
  • B2=4
  • B3=5
  • B4=5
  • B5=5
  • B6=5
  • BMUX=1
  • C=3
  • C1=4
  • C2=4
  • C3=4
  • C4=4
  • C5=4
  • C6=4
  • CLK=2
  • CQ=1
  • D=7
  • D1=3
  • D2=3
  • D3=5
  • D4=6
  • D5=7
  • D6=7
  • SR=2
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 75 74 0 0 0 0 0
bitgen 63 63 0 0 0 0 0
map 63 63 0 0 0 0 0
netgen 1 1 0 0 0 0 0
ngdbuild 67 67 0 0 0 0 0
par 62 62 0 0 0 0 0
trce 62 62 0 0 0 0 0
xst 113 113 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/spartan6/libs_le_acc16.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/test/uut/U_display PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2015-04-07T15:03:02 PROP_intWbtProjectID=F2F6E1184DFF449EA3C2570EA74F7386
PROP_intWbtProjectIteration=7 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.ftsd
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx16
PROP_DevFamilyPMName=spartan6 PROP_ISimSimulationRunTime_behav_tb=4000 ns
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=8
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=31 NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=24 NGDBUILD_NUM_LUT2=8
NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT4=5 NGDBUILD_NUM_LUT5=2 NGDBUILD_NUM_LUT6=21
NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_MUXF7=2 NGDBUILD_NUM_OBUF=35 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=25
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=31 NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=24
NGDBUILD_NUM_LUT2=8 NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT4=5 NGDBUILD_NUM_LUT5=2
NGDBUILD_NUM_LUT6=21 NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_MUXF7=2 NGDBUILD_NUM_OBUF=35
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=25
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=468 ms, 26460 KB
Total Signals=61
Total Nets=159
Total Blocks=10
Total Processes=44
Total Simulation Time=4 us
Simulation Resource Usage=1.9375 sec, 340369 KB
Simulation Mode=gui
Hardware CoSim=0