stopwatch Project Status
Project File: Lab5_1.xise Parser Errors: No Errors
Module Name: stopwatch Implementation State: Programming File Generated
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
19 Warnings (19 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 71 18,224 1%  
    Number used as Flip Flops 71      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 137 9,112 1%  
    Number used as logic 134 9,112 1%  
        Number using O6 output only 74      
        Number using O5 output only 54      
        Number using O5 and O6 6      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
    Number used exclusively as route-thrus 3      
        Number with same-slice register load 0      
        Number with same-slice carry load 3      
        Number with other load 0      
Number of occupied Slices 47 2,278 2%  
Number of MUXCYs used 68 4,556 1%  
Number of LUT Flip Flop pairs used 141      
    Number with an unused Flip Flop 71 141 50%  
    Number with an unused LUT 4 141 2%  
    Number of fully used LUT-FF pairs 66 141 46%  
    Number of unique control sets 3      
    Number of slice register sites lost
        to control set restrictions
9 18,224 1%  
Number of bonded IOBs 38 232 16%  
    Number of LOCed IOBs 38 38 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.19      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent週五 四月 10 14:27:06 2015019 Warnings (19 new)11 Infos (11 new)
Translation ReportCurrent週五 四月 10 14:27:18 2015000
Map ReportCurrent週五 四月 10 14:27:42 2015006 Infos (6 new)
Place and Route ReportCurrent週五 四月 10 14:27:50 2015003 Infos (3 new)
Power Report     
Post-PAR Static Timing ReportCurrent週五 四月 10 14:27:56 2015004 Infos (4 new)
Bitgen ReportCurrent週五 四月 10 14:28:06 2015000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent週五 四月 10 14:28:08 2015
WebTalk Log FileCurrent週五 四月 10 14:28:18 2015

Date Generated: 06/11/2015 -