Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) d96cc176c19a412192bec84ffaf3406b.F4076457403D422A83984B7F0255FB02.2 Target Package: csg324
Registration ID 210913348_0_0_143 Target Speed: -3
Date Generated 2015-04-05T00:10:17 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz CPU Speed 2494 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz CPU Speed 2494 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 25-bit adder=1
 Registers=33
  • Flip-Flops=33
 		MiscellaneousStatistics
  • AGG_BONDED_IO=12
  • AGG_IO=12
  • AGG_LOCED_IO=12
  • AGG_SLICE=8
  • NUM_BONDED_IOB=12
  • NUM_BSFULL=29
  • NUM_BSUSED=29
  • NUM_BUFG=1
  • NUM_LOCED_IOB=12
  • NUM_LOGIC_O5ANDO6=1
  • NUM_LOGIC_O5ONLY=23
  • NUM_LOGIC_O6ONLY=1
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_DRIVES_FLOP=3
  • NUM_LUT_RT_EXO5=3
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O5=1
  • NUM_LUT_RT_O6=23
  • NUM_SLICEL=7
  • NUM_SLICEX=1
  • NUM_SLICE_CARRY4=7
  • NUM_SLICE_CONTROLSET=2
  • NUM_SLICE_CYINIT=55
  • NUM_SLICE_FF=33
  • NUM_UNUSABLE_FF_BELS=7
 		NetStatistics
  • NumNets_Active=56
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=1
  • NumNodesOfType_Active_BOUNCEIN=7
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=1
  • NumNodesOfType_Active_CLKPIN=8
  • NumNodesOfType_Active_CLKPINFEED=1
  • NumNodesOfType_Active_CNTRLPIN=8
  • NumNodesOfType_Active_DOUBLE=15
  • NumNodesOfType_Active_GENERIC=15
  • NumNodesOfType_Active_GLOBAL=9
  • NumNodesOfType_Active_INPUT=7
  • NumNodesOfType_Active_IOBIN2OUT=11
  • NumNodesOfType_Active_IOBOUTPUT=11
  • NumNodesOfType_Active_LUTINPUT=32
  • NumNodesOfType_Active_OUTBOUND=39
  • NumNodesOfType_Active_OUTPUT=40
  • NumNodesOfType_Active_PADINPUT=8
  • NumNodesOfType_Active_PADOUTPUT=4
  • NumNodesOfType_Active_PINBOUNCE=15
  • NumNodesOfType_Active_PINFEED=57
  • NumNodesOfType_Active_QUAD=19
  • NumNodesOfType_Active_REGINPUT=3
  • NumNodesOfType_Active_SINGLE=29
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=6
  • IOB-IOBS=6
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=7
  • FF_SR=4
  • HARD0=1
  • INVERTER=1
  • IOB=12
  • IOB_IMUX=4
  • IOB_INBUF=4
  • IOB_OUTBUF=8
  • LUT5=28
  • LUT6=26
  • PAD=12
  • REG_SR=29
  • SLICEL=7
  • SLICEX=1
 
Configuration Data
FF_SR
  • CK=[CK:4] [CK_INV:0]
  • SRINIT=[SRINIT0:2] [SRINIT1:2]
  • SYNC_ATTR=[ASYNC:4]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:8]
  • SLEW=[SLOW:8]
  • SUSPEND=[3STATE:8]
 REG_SR
  • CK=[CK:29] [CK_INV:0]
  • LATCH_OR_FF=[FF:29]
  • SRINIT=[SRINIT0:27] [SRINIT1:2]
  • SYNC_ATTR=[ASYNC:29]
 SLICEL
  • CLK=[CLK:7] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:1] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=6
  • CO3=6
  • CYINIT=1
  • DI0=6
  • DI1=6
  • DI2=6
  • DI3=6
  • O0=7
  • O1=6
  • O2=6
  • O3=6
  • S0=7
  • S1=6
  • S2=6
  • S3=6
 FF_SR
  • CK=4
  • D=4
  • Q=4
  • SR=4
 HARD0
  • 0=1
 INVERTER
  • IN=1
  • OUT=1
 IOB
  • I=4
  • O=8
  • PAD=12
 IOB_IMUX
  • I=3
  • I_B=1
  • OUT=4
 IOB_INBUF
  • OUT=4
  • PAD=4
 IOB_OUTBUF
  • IN=8
  • OUT=8
 LUT5
  • A2=1
  • A5=3
  • O5=28
 LUT6
  • A3=1
  • A4=26
  • A5=1
  • A6=25
  • O6=26
 PAD
  • PAD=12
 REG_SR
  • CK=29
  • D=29
  • Q=29
  • SR=29
 SLICEL
  • A4=7
  • A6=6
  • AQ=7
  • B4=6
  • B6=6
  • BQ=6
  • C4=6
  • C6=6
  • CIN=6
  • CLK=7
  • COUT=6
  • CQ=6
  • D4=6
  • D6=6
  • DQ=6
  • SR=7
 SLICEX
  • A5=1
  • AMUX=1
  • AQ=1
  • AX=1
  • B5=1
  • BMUX=1
  • BQ=1
  • BX=1
  • C5=1
  • CLK=1
  • CMUX=1
  • CQ=1
  • CX=1
  • D2=1
  • D3=1
  • D4=1
  • D5=1
  • D6=1
  • DMUX=1
  • DQ=1
  • SR=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 47 46 0 0 0 0 0
bitgen 39 39 0 0 0 0 0
map 39 39 0 0 0 0 0
netgen 1 1 0 0 0 0 0
ngdbuild 42 42 0 0 0 0 0
par 39 39 0 0 0 0 0
trce 39 39 0 0 0 0 0
xst 75 75 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/spartan6/libs_le_acc16.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2015-04-01T20:06:32
PROP_intWbtProjectID=F4076457403D422A83984B7F0255FB02 PROP_intWbtProjectIteration=2
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx16 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=29 NGDBUILD_NUM_FDP=4 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=24 NGDBUILD_NUM_LUT3=1
NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=25
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=29 NGDBUILD_NUM_FDP=4 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=24
NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=25
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5