Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) d96cc176c19a412192bec84ffaf3406b.AB2602AA7D894B179B896BC31D2A681C.1 Target Package: csg324
Registration ID 210913348_0_0_143 Target Speed: -3
Date Generated 2015-04-05T21:16:53 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz CPU Speed 2494 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz CPU Speed 2494 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 24-bit adder=1
 Multiplexers=5
  • 1-bit 2-to-1 multiplexer=4
  • 1-bit 4-to-1 multiplexer=1
 RAMs=1
  • 4x4-bit single-port distributed Read Only RAM=1
 Registers=28
  • Flip-Flops=28
 		MiscellaneousStatistics
  • AGG_BONDED_IO=25
  • AGG_IO=25
  • AGG_LOCED_IO=25
  • AGG_SLICE=12
  • NUM_BONDED_IOB=25
  • NUM_BSFULL=28
  • NUM_BSLUTONLY=6
  • NUM_BSUSED=34
  • NUM_BUFG=1
  • NUM_LOCED_IOB=25
  • NUM_LOGIC_O5ANDO6=4
  • NUM_LOGIC_O5ONLY=22
  • NUM_LOGIC_O6ONLY=7
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=22
  • NUM_SLICEL=6
  • NUM_SLICEX=6
  • NUM_SLICE_CARRY4=6
  • NUM_SLICE_CONTROLSET=3
  • NUM_SLICE_CYINIT=61
  • NUM_SLICE_FF=28
  • NUM_SLICE_UNUSEDCTRL=4
  • NUM_UNUSABLE_FF_BELS=12
 		NetStatistics
  • NumNets_Active=74
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEIN=7
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=2
  • NumNodesOfType_Active_CLKPIN=8
  • NumNodesOfType_Active_CLKPINFEED=2
  • NumNodesOfType_Active_CNTRLPIN=9
  • NumNodesOfType_Active_DOUBLE=34
  • NumNodesOfType_Active_GENERIC=23
  • NumNodesOfType_Active_GLOBAL=10
  • NumNodesOfType_Active_INPUT=6
  • NumNodesOfType_Active_IOBIN2OUT=17
  • NumNodesOfType_Active_IOBOUTPUT=17
  • NumNodesOfType_Active_LUTINPUT=65
  • NumNodesOfType_Active_OUTBOUND=47
  • NumNodesOfType_Active_OUTPUT=44
  • NumNodesOfType_Active_PADINPUT=12
  • NumNodesOfType_Active_PADOUTPUT=6
  • NumNodesOfType_Active_PINBOUNCE=11
  • NumNodesOfType_Active_PINFEED=94
  • NumNodesOfType_Active_QUAD=19
  • NumNodesOfType_Active_SINGLE=35
  • NumNodesOfType_Vcc_GENERIC=7
  • NumNodesOfType_Vcc_HVCCOUT=16
  • NumNodesOfType_Vcc_IOBIN2OUT=7
  • NumNodesOfType_Vcc_IOBOUTPUT=7
  • NumNodesOfType_Vcc_LUTINPUT=26
  • NumNodesOfType_Vcc_PADINPUT=7
  • NumNodesOfType_Vcc_PINFEED=33
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=14
  • IOB-IOBS=11
  • SLICEX-SLICEL=2
  • SLICEX-SLICEM=1
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=6
  • HARD0=1
  • INVERTER=1
  • IOB=25
  • IOB_IMUX=6
  • IOB_INBUF=6
  • IOB_OUTBUF=19
  • LUT5=26
  • LUT6=34
  • PAD=25
  • REG_SR=28
  • SLICEL=6
  • SLICEX=6
 
Configuration Data
IOB_OUTBUF
  • DRIVEATTRBOX=[12:19]
  • SLEW=[SLOW:19]
  • SUSPEND=[3STATE:19]
 REG_SR
  • CK=[CK:28] [CK_INV:0]
  • LATCH_OR_FF=[FF:28]
  • SRINIT=[SRINIT0:26] [SRINIT1:2]
  • SYNC_ATTR=[ASYNC:28]
 SLICEL
  • CLK=[CLK:6] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:2] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=5
  • CO3=5
  • CYINIT=1
  • DI0=6
  • DI1=6
  • DI2=6
  • DI3=5
  • O0=6
  • O1=6
  • O2=6
  • O3=6
  • S0=6
  • S1=6
  • S2=6
  • S3=6
 HARD0
  • 0=1
 INVERTER
  • IN=1
  • OUT=1
 IOB
  • I=6
  • O=19
  • PAD=25
 IOB_IMUX
  • I=5
  • I_B=1
  • OUT=6
 IOB_INBUF
  • OUT=6
  • PAD=6
 IOB_OUTBUF
  • IN=19
  • OUT=19
 LUT5
  • A3=1
  • A4=3
  • A5=3
  • O5=26
 LUT6
  • A1=4
  • A2=4
  • A3=6
  • A4=34
  • A5=10
  • A6=33
  • O6=34
 PAD
  • PAD=25
 REG_SR
  • CE=2
  • CK=28
  • D=28
  • Q=28
  • SR=28
 SLICEL
  • A4=6
  • A6=6
  • AQ=6
  • B4=6
  • B6=6
  • BQ=6
  • C4=6
  • C6=6
  • CIN=5
  • CLK=6
  • COUT=5
  • CQ=6
  • D4=6
  • D6=5
  • DQ=6
  • SR=6
 SLICEX
  • A=2
  • A1=2
  • A2=2
  • A3=2
  • A4=4
  • A5=4
  • A6=4
  • AMUX=1
  • AQ=2
  • B=1
  • B3=1
  • B4=2
  • B5=2
  • B6=2
  • BMUX=1
  • BQ=1
  • C1=1
  • C2=1
  • C3=1
  • C4=1
  • C5=1
  • C6=1
  • CE=1
  • CLK=2
  • CQ=1
  • D=3
  • D1=1
  • D2=1
  • D3=2
  • D4=3
  • D5=3
  • D6=3
  • DMUX=1
  • SR=2
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 60 59 0 0 0 0 0
bitgen 51 51 0 0 0 0 0
map 50 50 0 0 0 0 0
netgen 1 1 0 0 0 0 0
ngdbuild 54 54 0 0 0 0 0
par 50 50 0 0 0 0 0
trce 50 50 0 0 0 0 0
xst 95 95 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/spartan6/libs_le_acc16.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2015-04-05T17:31:03
PROP_intWbtProjectID=AB2602AA7D894B179B896BC31D2A681C PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=false PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx16 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=5
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=25 NGDBUILD_NUM_FDCE=1 NGDBUILD_NUM_FDP=1
NGDBUILD_NUM_FDPE=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=5 NGDBUILD_NUM_INV=2
NGDBUILD_NUM_LUT1=23 NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_LUT3=4 NGDBUILD_NUM_LUT4=1
NGDBUILD_NUM_LUT6=4 NGDBUILD_NUM_MUXCY=23 NGDBUILD_NUM_OBUF=19 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=24
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=25 NGDBUILD_NUM_FDCE=1 NGDBUILD_NUM_FDP=1
NGDBUILD_NUM_FDPE=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=5 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=23 NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_LUT3=4
NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_LUT6=4 NGDBUILD_NUM_MUXCY=23 NGDBUILD_NUM_OBUF=19
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=24
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5