| binary_counter Project Status (04/03/2015 - 14:47:05) | |||
| Project File: | Lab3_bonus.xise | Parser Errors: | No Errors |
| Module Name: | binary_counter | Implementation State: | Synthesized |
| Target Device: | xc6slx16-3csg324 |
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No Errors |
| Product Version: | ISE 14.7 |
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10 Warnings (0 new) |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice Registers | 31 | 18224 | 0% | |
| Number of Slice LUTs | 49 | 9112 | 0% | |
| Number of fully used LUT-FF pairs | 31 | 49 | 63% | |
| Number of bonded IOBs | 21 | 232 | 9% | |
| Number of BUFG/BUFGCTRLs | 1 | 16 | 6% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 週五 四月 3 14:47:03 2015 | 0 | 10 Warnings (0 new) | 3 Infos (0 new) | |
| Translation Report | Out of Date | 週二 三月 31 20:38:55 2015 | 0 | 0 | 0 | |
| Map Report | Out of Date | 週二 三月 31 20:39:03 2015 | 0 | 0 | 6 Infos (6 new) | |
| Place and Route Report | Out of Date | 週二 三月 31 20:39:11 2015 | 0 | 0 | 3 Infos (3 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Out of Date | 週二 三月 31 20:39:15 2015 | 0 | 0 | 4 Infos (4 new) | |
| Bitgen Report | Out of Date | 週二 三月 31 20:39:22 2015 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Out of Date | 週二 三月 31 20:39:22 2015 | |
| WebTalk Log File | Out of Date | 週二 三月 31 20:39:30 2015 | |