Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) d96cc176c19a412192bec84ffaf3406b.F31FAED3658640D8B5CF51F85916B1BF.1 Target Package: csg324
Registration ID 210913348_0_0_143 Target Speed: -3
Date Generated 2015-03-22T15:45:57 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz CPU Speed 2494 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7-4710HQ CPU @ 2.50GHz CPU Speed 2494 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 25-bit adder=1
 Registers=25
  • Flip-Flops=25
 		MiscellaneousStatistics
  • AGG_BONDED_IO=3
  • AGG_IO=3
  • AGG_LOCED_IO=3
  • AGG_SLICE=7
  • NUM_BONDED_IOB=3
  • NUM_BSFULL=25
  • NUM_BSUSED=25
  • NUM_BUFG=1
  • NUM_LOCED_IOB=3
  • NUM_LOGIC_O5ANDO6=1
  • NUM_LOGIC_O5ONLY=23
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=23
  • NUM_SLICEL=7
  • NUM_SLICE_CARRY4=7
  • NUM_SLICE_CONTROLSET=1
  • NUM_SLICE_CYINIT=50
  • NUM_SLICE_FF=25
  • NUM_UNUSABLE_FF_BELS=7
 		NetStatistics
  • NumNets_Active=37
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEIN=6
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=1
  • NumNodesOfType_Active_CLKPIN=7
  • NumNodesOfType_Active_CLKPINFEED=1
  • NumNodesOfType_Active_CNTRLPIN=7
  • NumNodesOfType_Active_GENERIC=4
  • NumNodesOfType_Active_GLOBAL=9
  • NumNodesOfType_Active_INPUT=7
  • NumNodesOfType_Active_IOBIN2OUT=2
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_LUTINPUT=25
  • NumNodesOfType_Active_OUTBOUND=27
  • NumNodesOfType_Active_OUTPUT=32
  • NumNodesOfType_Active_PADINPUT=1
  • NumNodesOfType_Active_PADOUTPUT=2
  • NumNodesOfType_Active_PINBOUNCE=6
  • NumNodesOfType_Active_PINFEED=41
  • NumNodesOfType_Active_QUAD=9
  • NumNodesOfType_Active_SINGLE=18
 SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=1
  • IOB-IOBS=2
 		SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=7
  • HARD0=1
  • INVERTER=1
  • IOB=3
  • IOB_IMUX=2
  • IOB_INBUF=2
  • IOB_OUTBUF=1
  • LUT5=24
  • LUT6=25
  • PAD=3
  • REG_SR=25
  • SLICEL=7
 
Configuration Data
IOB_OUTBUF
  • DRIVEATTRBOX=[12:1]
  • SLEW=[SLOW:1]
  • SUSPEND=[3STATE:1]
 REG_SR
  • CK=[CK:25] [CK_INV:0]
  • LATCH_OR_FF=[FF:25]
  • SRINIT=[SRINIT0:25]
  • SYNC_ATTR=[ASYNC:25]
 SLICEL
  • CLK=[CLK:7] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
 BUFG_BUFG
  • I0=1
  • O=1
 CARRY4
  • CIN=6
  • CO3=6
  • CYINIT=1
  • DI0=6
  • DI1=6
  • DI2=6
  • DI3=6
  • O0=7
  • O1=6
  • O2=6
  • O3=6
  • S0=7
  • S1=6
  • S2=6
  • S3=6
 HARD0
  • 0=1
 INVERTER
  • IN=1
  • OUT=1
 IOB
  • I=2
  • O=1
  • PAD=3
 IOB_IMUX
  • I=1
  • I_B=1
  • OUT=2
 IOB_INBUF
  • OUT=2
  • PAD=2
 IOB_OUTBUF
  • IN=1
  • OUT=1
 LUT5
  • O5=24
 LUT6
  • A4=25
  • A6=24
  • O6=25
 PAD
  • PAD=3
 REG_SR
  • CK=25
  • D=25
  • Q=25
  • SR=25
 SLICEL
  • A4=7
  • A6=6
  • AQ=7
  • B4=6
  • B6=6
  • BQ=6
  • C4=6
  • C6=6
  • CIN=6
  • CLK=7
  • COUT=6
  • CQ=6
  • D4=6
  • D6=6
  • DQ=6
  • SR=7
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • netgen -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim <fname>.ngc <fname>.v
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 11 11 0 0 0 0 0
bitgen 9 9 0 0 0 0 0
map 9 9 0 0 0 0 0
netgen 1 1 0 0 0 0 0
ngdbuild 9 9 0 0 0 0 0
par 9 9 0 0 0 0 0
trce 9 9 0 0 0 0 0
xst 15 15 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/spartan6/libs_le_acc16.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2015-03-22T15:13:12
PROP_intWbtProjectID=F31FAED3658640D8B5CF51F85916B1BF PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx16
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=csg324
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=25 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=24 NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_OBUF=1
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=25
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=25 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=24 NGDBUILD_NUM_MUXCY=24
NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=25
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5