top Project Status (05/25/2015 - 11:24:42)
Project File:	Lab10_2.xise	Parser Errors:	No Errors
Module Name:	top	Implementation State:	Synthesized (Stopped)
Target Device:	xc6slx16-3csg324	Errors:
Product Version:	ISE 14.7	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	¶g¤@ ¤­¤ë 25 11:24:34 2015	0	0	0
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 05/25/2015 - 11:24:54