lab1_2_DecimalAdder Project Status
Project File:	Lab1.xise	Parser Errors:	No Errors
Module Name:	lab1_2_DecimalAdder	Implementation State:	Synthesized
Target Device:	xc6slx16-3csg324	Errors:	X 1 Error (1 new)
Product Version:	ISE 14.7	Warnings:	1 Warning (1 new)
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	週二 三月 10 12:40:55 2015	X 1 Error (1 new)	1 Warning (1 new)	0
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Current	週二 三月 10 12:42:11 2015

Date Generated: 04/14/2015 - 02:29:06